DETAILED ACTION
Status of Application
Claims 1-2, 4-8, 10, 13-14, and 17-25 are pending in the present application.
Response to Arguments
Applicant's arguments filed 12/26/2025 have been fully considered but they are not persuasive. The reasons set forth below.
Applicant argues: (1) Jagtap does no teach performing a context switch of a PIM state, but instead, only detects that a context switch has previously occurred [remarks, pp. 9-10]; (2) Dalal does not teach a memory controller that performs any context switching, let alone a context switch of a PIM state [remarks, p. 10]; (3) Khan fails to teach a memory controller configured to perform a context switch of a PIM state and performing such a context switch based on a second process being active on a PIM device [remarks, p. 10].
The examiner respectfully disagrees with these arguments.
Regarding the first argument, applicant argues that paragraph 38 of Jagtap states, the control circuitry may not see the execution context switch until some time after the corresponding switch at the processing element [remarks, p. 10]. The examiner notes that paragraphs 18, 84, fig. 1, and fig. 4 of Jagtap were used to teach the limitation in question. "The control circuitry has interface circuitry to receive memory access requests to be serviced by the memory and to provide responses to memory access requests that have been serviced by the memory. The control circuitry also has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context"; "another way of identifying when there is a switch of execution context among the memory access requests being handled by the memory may be to use a context switch barrier indication 60 which can be included in a stream of memory access requests"; also see fig. 4 showing receiving from 4, a request at 30 to switch context]. Applicant is silent on the examiner’s citation of Jagtap, specifically the use of a switch barrier indication included in the memory access request(s). As shown above, Jagtap discloses the control circuitry receiving memory access requests. Jagtap discloses handling the memory access request with request handling circuitry. Jagtap discloses using a context switch barrier indication included in the memory access request to perform a context switch such that the switch barrier indication 60 marks the point at which the requests beyond the barrier relate to a different execution context to the requests before the barrier. Hence, it is quite clear that a context switch is performed so that requests relating to a second execution context can be serviced.
Regarding the second argument, the examiner notes that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, Jagtap discloses the memory controller and context switch, however applicant argues that Dalal does not teach a memory controller and context switch. This argument cannot show nonobviousness because it attacks the references individually, where the rejection is based on the combination of Jagtap and Dalal.
In addition, applicant is silent on the examiner’s cited portions of Dalal [Dalal, paragraphs 20, 22, 67, figs. 2-0, 2-1, 2-2, and fig. 1-0]. Applicant has not provided specific arguments as to how Dalal does not teach the claim limitation(s) of a PIM command, PIM state, PIM device. Therefore, the prior art rejection is maintained.
Regarding the third argument, the examiner notes that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, Jagtap in combination with Dalal discloses the memory controller configured to perform a context switch of a PIM state. Applicant argues that Khan does not teach these elements, however this argument cannot show nonobviousness because it attacks the references individually, where the rejection is based on the combination of Jagtap and Dalal.
In addition, applicant is silent on the examiner’s cited portions of Khan [Khan, paragraph 30]. Applicant has not provided specific arguments as to how Khan does not teach the claim limitation(s) of a context switch based on a second process being active on a PIM device. Therefore, the prior art rejection is maintained.
In regards to claims 10-12, 17-18, 20, and 24, applicant has not provided specific arguments as to how the language of the claims patentably distinguishes them from the references. Therefore, the prior art rejection is maintained.
The examiner acknowledges applicant’s statement regarding claim 26. The examiner notes that claim 26 was inadvertently omitted from the 35 U.S.C. 103 claim rejection header only. Claim 26 was rejected on page 9-11 of the Non-Final Rejection. The instant Office Action includes a corrected header. The prior art relied upon, and the rationale supporting the rejection, is the same under as presented in the Non-Final Rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 13, and 26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 10, and 17, respectively, of U.S. Patent No. 11,934,827 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 11,934,827 B2
Claim 1. An apparatus comprising:
a memory controller configured to:
perform, in response to receiving a processing-in-memory (PIM) command from a first process, a context switch of a PIM state based on a second process being active on a PIM device; and
issue the PIM command of the requesting first process to the PIM device.
Claim 1. An apparatus configured for managing multi-process execution in a processing-in-memory (PIM) device, the apparatus comprising a memory controller, the memory controller comprising logic configured to:
receive, from a first process, a memory request that includes a PIM command;
perform a context switch of a PIM state based on the first process being a registered PIM process and a second process being a registered PIM process and being active on the PIM device; and
issue the PIM command of the first process to the PIM device.
Claims 2 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 10, respectively, of U.S. Patent No. 11,934,827 B2.
Claims 4-7, 10, and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-6, 8, and 13-15, respectively, of U.S. Patent No. 11,934,827 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jagtap et al (hereinafter Jagtap), US 20190384501 A1, in view of Dalal et al (hereinafter Dalal), US 20140201402 A1, and further in view of Khan et al (hereinafter Khan), US 20040268071 A1.
Referring to claims 1 and 13, taking claim 1 as exemplary, Jagtap discloses an apparatus comprising:
a memory controller [fig. 1, paragraph 18, “For example the control circuitry could be a portion of an interconnect or a memory controller”; memory controller 14 with control circuitry 16] configured to:
perform, in response to receiving a command from a first process a context switch [fig. 1, paragraphs 18, 84, “The control circuitry has interface circuitry to receive memory access requests to be serviced by the memory and to provide responses to memory access requests that have been serviced by the memory. The control circuitry also has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context”; “another way of identifying when there is a switch of execution context among the memory access requests being handled by the memory may be to use a context switch barrier indication 60 which can be included in a stream of memory access requests”; also see fig. 4 showing receiving from 4, a request at 30 to switch context]; and
issue the command of the first process to the device [fig. 4, see control 16 outputting the request from element 36; fig. 1 showing the architecture and therefore the request being sent to DRAM; paragraphs 18, 84, “The control circuitry has interface circuitry to receive memory access requests to be serviced by the memory and to provide responses to memory access requests that have been serviced by the memory”].
Jagtap does not explicitly disclose the command as a processing-in-memory (PIM) command;
the context switch of a PIM state; and
a PIM device.
However, Dalal discloses the command as a processing-in-memory (PIM) command [paragraphs 20, 22, “A scheduler 116 can coordinate context switches of offload processors 118 based on received processing requests”; “Data and processing tasks for execution by offload processors 118 can be received over memory bus 124”];
the context switch of a PIM state [paragraph 67, “In particular embodiments, according to scheduler 216, switch controller 218 can order offload processor(s) 208 to switch contexts”; performing a context switch of a PIM device’s state such as device 200]; and
a PIM device [figs. 2-0, 2-1, 2-2, and fig. 1-0 with in-line memory module 122].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dalal in the apparatus of Jagtap to implement, the command as a processing-in-memory (PIM) command; the context switch of a PIM state; and a PIM device, in order to improve overall system performance and reduce hardware and power requirements [Dalal, paragraph 4].
The modified Jagtap does not explicitly disclose the context switch based on a second process being active on a PIM device.
However, Khan discloses the context switch based on a second process being active on a PIM device [paragraph 30, “A context switch event may occur when an active period of one process comes to an end, and an active period of another process is scheduled to begin”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Khan in the apparatus of Jagtap to implement, the context switch based on a second process being active on a PIM device, in order to increasing the efficiency of address translations and reduce or avoid overhead [Khan, paragraph 2].
Referring to claim 26, Jagtap discloses a system comprising:
a device [fig. 1, DRAM and/or NVRAM]; and
a processor [fig. 1, element 4]; and
a memory controller [fig. 1, element 14] coupled to the processor and the device [fig. 1], the memory controller configured to:
perform, in response to receiving a command from a first process, a context switch [fig. 1, paragraphs 18, 84, “The control circuitry has interface circuitry to receive memory access requests to be serviced by the memory and to provide responses to memory access requests that have been serviced by the memory. The control circuitry also has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context”; “another way of identifying when there is a switch of execution context among the memory access requests being handled by the memory may be to use a context switch barrier indication 60 which can be included in a stream of memory access requests”; also see fig. 4 showing receiving from 4, a request at 30 to switch context]; and
issue the PIM command of the first process to the device [fig. 4, see control 16 outputting the request from element 36; fig. 1 showing the architecture and therefore the request being sent to DRAM; paragraphs 18, 84, “The control circuitry has interface circuitry to receive memory access requests to be serviced by the memory and to provide responses to memory access requests that have been serviced by the memory”].
Jagtap does not explicitly disclose a processing-in-memory (PIM) device;
the command command as a processing-in-memory (PIM) command;
the context switch of a PIM state.
However, Dalal discloses a processing-in-memory (PIM) device [figs. 2-0, 2-1, 2-2, and fig. 1-0 with in-line memory module 122];
the command as a processing-in-memory (PIM) command [paragraphs 20, 22, “A scheduler 116 can coordinate context switches of offload processors 118 based on received processing requests”; “Data and processing tasks for execution by offload processors 118 can be received over memory bus 124”];
the context switch of a PIM state [paragraph 67, “In particular embodiments, according to scheduler 216, switch controller 218 can order offload processor(s) 208 to switch contexts”; performing a context switch of a PIM device’s state such as device 200].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dalal in the system of Jagtap to implement, a processing-in-memory (PIM) device; the command command as a processing-in-memory (PIM) command; the context switch of a PIM state, in order to improve overall system performance and reduce hardware and power requirements [Dalal, paragraph 4].
The modified Jagtap does not explicitly disclose the context switch based on a second process being active on a PIM device.
However, Khan discloses the context switch based on a second process being active on a PIM device [paragraph 30, “A context switch event may occur when an active period of one process comes to an end, and an active period of another process is scheduled to begin”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Khan in the system of the modified Jagtap to implement, the context switch based on a second process being active on a PIM device, in order to increasing the efficiency of address translations and reduce or avoid overhead [Khan, paragraph 2].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jagtap, in view of Dalal, in view of Khan, as applied to claim 1 above, and further in view of Kim et al (hereinafter Kim), “Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests” (disclosed on IDS filed on 03/11/2024).
Referring to claim 10, the modified Jagtap does not explicitly disclose the apparatus of claim 1, wherein the memory controller is configured to process non-PIM memory requests concurrently with memory requests that include a PIM command.
However, Kim discloses wherein the memory controller is configured to process non-PIM memory requests concurrently with memory requests that include a PIM command [p. 252, col. 1, By preserving both the DRAM standard operation semantics and their timing constraints, we could execute both PIM and non-PIM applications simultaneously].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kim in the apparatus of the modified Jagtap to implement, wherein the memory controller is configured to process non-PIM memory requests concurrently with memory requests that include a PIM command, in order to provide PIM computation requiring no change of hardware components [Kim, p. 252, col. 1].
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jagtap, in view of Dalal, in view of Khan, as applied to claim 13 above, and further in view of Harvey et al (hereinafter Harvey), U.S. Patent No. 6,233,668 B1.
Referring to claim 17, the modified Jagtap does not explicitly disclose the method of claim 13, further comprising:
queueing the PIM command prior to performing the context switch of the PIM state.
However, Harvey discloses queueing the PIM command prior to performing the context switch of the PIM state [col. 2, lines 8-22, When the central processing unit 12 turns to a new process after having completed a previous process's time slice, it performs a "context switch."; processes that are awaiting their turn via time slice are queued].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Harvey in the method of the modified Jagtap to implement, queueing the PIM command prior to performing the context switch of the PIM state, in order to provide concurrent processing so as to maximize processor utilization [Harvey, col. 2, lines 8-11].
Referring to claim 18, the modified Jagtap does not explicitly disclose the method of claim 13, wherein the PIM command is queued for a predefined period of time before performing the context switch.
However, Harvey discloses wherein the PIM command is queued for a predefined period of time before performing the context switch [Harvey, col. 2, lines 8-22, expiration of time slice timer].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Harvey in the method of the modified Jagtap to implement, wherein the PIM command is queued for a predefined period of time before performing the context switch, in order to provide concurrent processing so as to maximize processor utilization [Harvey, col. 2, lines 8-11].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jagtap, in view of Dalal, in view of Khan, as applied to claim 13 above, and further in view of Wang et al (hereinafter Wang), US 20130305259 A1.
Referring to claim 20, the modified Jagtap does not explicitly disclose the method of claim 13, wherein the PIM command is associated with an identification of the requesting first process; and wherein the context switch of the PIM state is performed based on the identification of the first process not matching an identification of the second process.
However, Wang discloses wherein the PIM command is associated with an identification of the requesting first process; and wherein the context switch of the PIM state is performed based on the identification of the first process not matching an identification of the second process [fig. 1, S104, “when the identification of the process requiring access to the hardware device and the identification of the previous process accessed the hardware device are different, a context switch is performed”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Wang in the method of the modified Jagtap to implement, wherein the PIM command is queued for a predefined period of time before performing the context switch, in order to provide concurrent processing so as to maximize processor utilization [Harvey, col. 2, lines 8-11].
Claim(s) 21 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jagtap, in view of Dalal, in view of Khan, as applied to claims 1 and 13 above, and further in view of Gonion, US 20060004996 A1.
Referring to claims 21 and 24, taking claim 21 as exemplary, the modified Jagtap does not explicitly disclose the apparatus of claim 1, wherein the context switch of the PIM state includes a context switch of a PIM orchestration context.
However, Gonion discloses wherein the context switch of the PIM state includes a context switch of a PIM orchestration context [paragraph 273, “When a context switch occurs, for example, from process 2307 to one of the other processes 2309, the supervisor mode software 2308 may access the register files 2317 to save all of the values of registers in the register files 2317 in the memory 2310 before performing the context switch. Thereafter, when another context switch occurs from one of the other processes 2309 back to process 2307, the supervisor mode software 2308 may access the register files 2317 again to restore the values of the registers in the register files 2317”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Gonion in the apparatus of the modified Jagtap to implement, wherein the context switch of the PIM state includes a context switch of a PIM orchestration context, in order to improve efficiency and performance while reducing power dissipation [Gonion, paragraph 69].
Allowable Subject Matter
Claims 2, 4-8, 14, 19, 22-23, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the double patenting rejection is overcome.
Claims 4-8 are objected to by virtue of their dependency.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the context switch of the PIM state includes a context switch of a PIM orchestration context and a PIM configuration context, in combination with other recited limitations in claim 22.
Claim 23 is objected to by virtue of its dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the context switch of the PIM state includes a context switch of a PIM orchestration context and a PIM configuration context, in combination with other recited limitations in claim 25.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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/Farley Abad/Primary Examiner, Art Unit 2181