DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/11/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshinaga et al., CN 109557842
Regarding claim 1, Yoshinaga discloses a comparator circuit comprising: an amplifier including an auto zero operational amplifier(Fig. 2-3; auto zero amplifier circuit 12c) and amplifying a difference between an input voltage and a predetermined first voltage(fig. 3; input voltage difference between positive and negative terminal); and a first voltage comparator comparing an output voltage of the amplifier with a predetermined second voltage (fig. 2-3; comparator 12d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshinaga et al., CN 109557842 in view of Kasireddy et al., US 11811244
Regarding claim 2, Yoshinaga is silent in further comprising: a second voltage comparator comparing the output voltage of the amplifier with a predetermined third voltage, wherein the comparator circuit operates as a window comparator. Kasireddy teaches a second voltage comparator comparing the output voltage of the amplifier with a predetermined third voltage, wherein the comparator circuit operates as a window comparator (Col. 17 lines 3-6; comparator circuit 74 with first and second comparators with voltages Vsup, Vslo). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Kasireddy into Yoshinaga for the benefit of providing upper and lower limits for the signal detecting circuit.
Regarding claim 5, Yoshinaga teaches the comparator circuit according to claim 2; and a variable voltage source generating the first voltage having a voltage level corresponding to an expected value of the input voltage (Fig. 3; sw1 changes voltage level at non-inverting terminal of OP2 therefore is variable).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshinaga et al., CN 109557842 in view of Pan et al., CN 216051910
Regarding claim 3, Yoshinaga is silent wherein the first voltage comparator and the second voltage comparator have an output stage of an open collector or an open drain, and outputs of the first voltage comparator and the second voltage comparator are pulled up by a common resistance. Pan teaches wherein a first voltage comparator and a second voltage comparator have an output stage of an open collector or an open drain, and outputs of the first voltage comparator and the second voltage comparator are pulled up by a common resistance (Fig. 7; comparator 107, 108, resistors R3, R4 and switch K1, K2). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Pan into Yoshinaga for the benefit of providing a circuit for measuring current in the input with accuracy.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshinaga et al., CN 109557842 in view of Jiang et al., US 20130038388
Regarding claim 4, Yoshinaga is silent in wherein the amplifier is a subtraction circuit. Jiang teaches wherein the amplifier is a subtraction circuit (¶[0004]; Fig. 1; auto zero amp 150 subtracts signals). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Jiang into Yoshinaga for the benefit of cancelling out offset voltages to produce more accurate signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEBA POTHEN whose telephone number is (571)272-9219. The examiner can normally be reached 8:30-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on 571.272.2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FEBA POTHEN/Examiner, Art Unit 2858
Prosecution Insights