DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species A, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/7/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-3, 8-14, and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeda et al. (US 2015/0062212 A1) in view of Omata et al. (6062666).
Regarding claim 1:
Umeda et al. disclose a liquid discharge head substrate comprising:
a plurality of liquid discharge elements (heaters 302-n) constituting an element array (heater group 302) along a first direction (Fig. 6); and
a delay circuit (301) configured to generate a plurality of delay signals (HE-n) obtained by delaying an enable signal (heat enable HE) for driving the plurality of liquid discharge elements by different delay amounts (paragraph 60 & Figs. 6-7),
wherein the delay circuit includes a first circuit (buffer group 401) configured to start supplying delay signals selected from the plurality of delay signals to liquid discharge elements of the plurality of liquid discharge elements, which are included in a first liquid discharge element group (those of a first selected block: paragraphs 56, 66), sequentially in a forward direction in the first direction (paragraph 64 & Fig. 7A), and a second circuit (buffer group 402) configured to start supplying delay signals selected from the plurality of delay signals to liquid discharge elements of the plurality of liquid discharge elements, which are included in a second liquid discharge group different from the first liquid discharge element group (those of another selected block: paragraphs 56, 66) sequentially in a backward direction in the first direction (paragraph 64 & Fig. 7B).
Umeda et al. do not expressly disclose the particulars of the first and second element groups, and therefore do not expressly disclose that not less than one liquid discharge element of liquid discharge elements included in the first liquid discharge element group and no less than one liquid discharge element of the liquid discharge elements included in the second liquid discharge element group are alternately arranged.
However, Omata et al. disclose a liquid discharge head substrate that time-divisionally drives an element array of liquid discharge elements (heaters 802: Fig. 9), so as to disperse positions of print unevenness (col. 4, lines 10-23) by using at least a first liquid discharge element group (e.g. those of block BENB1) and a second discharge element group (e.g. those of block BENB2),
wherein, in the element array, not less than one liquid discharge element of liquid discharge elements included in the first liquid discharge element group and no less than one liquid discharge element of the liquid discharge elements included in the second liquid discharge element group are alternately arranged (any of Figs. 10, 12, 13, 15).
Therefore, at the time of filing, it would have been obvious to a person of ordinary skill in the art to modify Umeda et al.’s liquid discharge head substrate to utilize Omata et al.’s time-divisional driving techniques.
Regarding claim 2:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Umeda et al. also disclose that the first circuit starts supplying delay signals selected from the plurality of delay signals to all liquid discharge elements included in the first liquid discharge element group, and the second circuit then starts supplying delay signals selected from the plurality of delay signals to the liquid discharge elements included in the second liquid discharge element group (paragraph 66, 110 & Figs. 8).
Regarding claim 3:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Umeda et al. also disclose that the first circuit and the second circuit each include a plurality of buffer circuits (403), and the plurality of buffer circuits respectively supply outputs to corresponding liquid discharge elements of the plurality of liquid discharge elements (Figs. 6-7).
Regarding claim 8:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Omata et al. also disclose that input image data is arranged by including a plurality of memory elements (shift registers 803) respectively corresponding to the plurality of liquid discharge elements (Fig. 9) and configured to hold drive or non-drive information (“image data”) of the plurality of liquid discharge elements (col. 7, lines 34-39),
wherein the plurality of liquid discharge elements includes a first liquid discharge element (e.g. a topmost heater 802: Fig. 9),
wherein the information is written in each of the plurality of memory elements in a predetermined order starting from a memory element, of the plurality of memory elements, which corresponds to the first liquid discharge element (col. 7, lines 34-39 & Fig. 9); and
Umeda et al. also disclose that the plurality of liquid discharge elements includes a first liquid discharge element (e.g. an end-most heater 302a/g) to which a first delay signal (one of HE-g / HE-a) of the plurality of delay signals is supplied (Figs. 7, 8).
Therefore, at the time of filing, it would have been obvious to a person of ordinary skill in the art to include the memory elements taught by Omata et al. into Umeda et al.’s liquid discharge head substrate, so as to arrange input image data.
Regarding claim 9:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 8, and Omata et al. also disclose that the plurality of memory elements are arranged along the first direction (Fig. 9), and the information is written in the plurality of memory elements sequentially in the forward direction (such sequential writing is inherent to the shift register: col. 7, lines 34-39 & Fig. 9).
Regarding claim 10:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Umeda et al. also disclose that the enable signal is commonly supplied to the first circuit and the second circuit (Figs. 6-7).
Regarding claim 11:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Omata et al. also disclose that the delay circuit includes a third circuit (e.g. buffer circuit 401 of delay circuit 1304: Fig. 16) configured to start supplying delay signals selected from the plurality of delay signals, sequentially in the forward direction, to liquid discharge elements that are included in a third liquid discharge element group (those of a first selected block in heater group 1302: paragraphs 56, 66 & Fig. 16) different from the first liquid discharge element group and the second liquid discharge element group (Fig. 16), and a fourth circuit (e.g. buffer circuit 402 of delay circuit 1304: Fig. 16) configured to start supplying delay signals selected from the plurality of delay signals, sequentially in the backward direction (), to liquid discharge elements that are included in a fourth liquid discharge element group (those of another selected block in heater group 1302: paragraphs 56, 66 & Fig. 16) different from the first liquid discharge element group, the second liquid discharge element group, and the third liquid discharge element group (Figs. 16); and
Omata et al. also disclose using various liquid discharge element groups (those of blocks BENBn: Fig. 9),
wherein, in the element array, not less than one liquid discharge element of liquid discharge elements included in a third liquid discharge element group and no less than one liquid discharge element of the liquid discharge elements included in a fourth liquid discharge element group are alternately arranged (any of Figs. 10, 12, 13, 15).
Therefore, in Umeda et al.’s modified substrate, it would have been obvious to a person of ordinary skill in the art to utilize Omata et al.’s time-divisional driving to Umeda et al.’s third and fourth liquid discharge element groups.
Regarding claim 12:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 11, and Omata et al. also disclose that the element array is divided from a middle of the element array as a boundary into a portion in which the first liquid discharge element group and the second liquid discharge element group are arranged and a portion in which the third liquid discharge element group and the fourth liquid discharge element group are arranged (the BENb groups are symmetric about the middle of the element array: Fig. 15).
Regarding claim 13:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 11, and Umeda et al. also disclose that the enable signal is commonly supplied to the first circuit and the second circuit (Figs. 6-7).
Regarding claim 14:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 13, and Umeda et al. also disclose that the first circuit starts supplying delay signals selected from the plurality of delay signals to all liquid discharge elements included in the first liquid discharge element group, and the second circuit then starts supplying delay signals selected from the plurality of delay signals to the liquid discharge elements included in the second liquid discharge element group (paragraph 66, 110 & Figs. 8, 16).
Regarding claim 19:
Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Umeda et al. also disclose that the plurality of liquid discharge elements each are arranged between a common power line (VH) and a ground line (GNDH: Fig. 6).
Regarding claim 20: Umeda et al.’s modified liquid discharge head substrate comprises all the limitations of claim 1, and Umeda et al. also disclose that the liquid discharge head substrate is comprised in a liquid discharge head (printhead 14), the liquid discharge head also comprising a discharge port (orifice 601) from which discharge of liquid is controlled by the liquid discharge head substrate (Fig. 9).
Regarding claim 21:
Umeda et al.’s modified liquid discharge head comprises all the limitations of claim 20, and Umeda et al. also disclose that the liquid discharge head is comprised in a liquid discharge apparatus (Fig. 1), the liquid discharge apparatus also comprising a unit (head control substrate 109) configured to supply a driving signal for making the liquid discharge head discharge a liquid (paragraph 50).
Allowable Subject Matter
Claims 4-5 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 appears to contain allowable subject matter because the prior art of record does not expressly disclose or make obvious a first circuit and second circuit that “are connected in series in the delay circuit.” It is this limitation, in combination with other features and limitations of claim 4, that indicates allowable subject matter over the prior art of record.
Claim 5 appears to contain allowable subject matter because the prior art of record does not expressly disclose or make obvious a delay circuit in which “an output of a last-stage buffer circuit of the plurality of buffer circuits of the first circuit is input to the second circuit.” It is this limitation, in combination with other features and limitations of claim 5, that indicates allowable subject matter over the prior art of record.
Claim 15 appears to contain allowable subject matter because the prior art of record does not expressly disclose or make obvious a third circuit and a fourth circuit that “are connected in series in the delay circuit.” It is this limitation, in combination with other features and limitations of claim 15, that indicates allowable subject matter over the prior art of record.
Claim 16 appears to contain allowable subject matter because the prior art of record does not expressly disclose or make obvious a delay circuit in which “an output of a last-stage buffer circuit of the plurality of buffer circuits of the fourth circuit is input to the third circuit.” It is this limitation, in combination with other features and limitations of claim 16, that indicates allowable subject matter over the prior art of record.
Claims 17-18 appear to contain allowable subject matter because the prior art of record does not expressly disclose or make obvious a substrate comprising a second plurality of liquid discharge elements that include “a liquid discharge element included in a fifth liquid discharge element group sharing a delay signal, of the plurality of delay signals, which is supplied from the first circuit to the first liquid discharge element group.” It is this limitation, in combination with other features and limitations of claim 17, that indicates allowable subject matter over the prior art of record.
Communication with the USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shelby L Fidler whose telephone number is (571)272-8455. The examiner can normally be reached Monday-Friday, 8:30am - 5pm EST.
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SHELBY L. FIDLER
Primary Examiner
Art Unit 2853
/SHELBY L FIDLER/ Primary Examiner, Art Unit 2853