DETAILED ACTION
This office action is in response to the application filed on 03/11/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 4, 7, 10, 13-14. Therefore, all the limitations of each claim must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner’s Note: For claims 4 and 7 Vpwm is not shown in any of the operation graphs. Claim 10 operation is not shown in figures 7 or 8. Claims 13-14 show a relationship between the ramps when they meet or intersect which is also not shown in the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2 is objected to because of the following informalities: Claim 2 lines 4 and 7 recite “level till a voltage” this should be change to “level until a voltage”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 12-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miller US 2007/0273340
Regarding Claim 1, Miller teaches (Figures 1-6) a duty cycle control circuit (Fig. 3b) applicable to DC-DC buck conversion (22, buck mode), the duty cycle control circuit being capable of generating a duty cycle control signal (from 60 or 64) to control a duty cycle of an output signal (from 62 or 66) and comprising: a dual ramp generator (12 and Fig. 6 generating ramp1 and ramp2) configured to generate a first ramp signal and a second ramp signal (ramp1 and ramp2), wherein the first ramp signal and the second ramp signal have a same frequency but different phases (see fig. 4, ramp1 and ramp2); a first comparator (41) configured to compare the first ramp signal (ramp1) with a feedback signal (Ve) to generate a first control signal (comp1out); a second comparator (42) configured to compare the second ramp signal (ramp2) with the feedback signal (Ve) to generate a second control signal (comp2out); and a logical circuit (A-D, 60-64 and Fig. 6 circuitry) configured to perform a first predetermined logical operation (with D) according to a first signal (comp1out) and a first conduction-control signal (clkb) and thereby generate a first duty cycle control signal (Q4) as a first part of the duty cycle control signal (from 64), and further configured to perform a second predetermined logical operation (with C) according to a second signal (comp2out) and a second conduction-control signal (clk) and thereby generate a second duty cycle control signal (Q3) as a second part of the duty cycle control signal (from 64), wherein the first signal is the first control signal (comp1out) or an inversion of the first control signal, and the second signal is the second control signal (comp2out) or an inversion of the second control signal. (For Example: Par. 34-40 and 47-52)
Regarding Claim 2, Miller teaches (Figures 1-6) wherein when a voltage level of the second ramp signal (ramp2, Fig. 4) reaches a minimum voltage level of the second ramp signal (Fig. 4, bottom level), a voltage level of the first conduction-control signal (clkb) changes from low to high (clkb high)and then is kept at a first high voltage level until a voltage level of the first ramp signal (ramp1) reaches a maximum voltage level of the first ramp signal (clkb low); and when the voltage level of the first ramp signal (ramp1) reaches a minimum voltage level (bottom level in Fig. 4) of the first ramp signal, a voltage level of the second conduction-control signal (clk) changes from low to high (clk high) and then is kept at a second high voltage level till the voltage level of the second ramp signal reaches a maximum voltage level (clk low) of the second ramp signal (ramp2). (For Example: Par. 34-40 and 47-52)
Regarding Claim 3, Miller teaches (Figures 1-6) wherein when the first signal is the first control signal (comp1out) and the second signal is the second control signal (comp2out), each of the first predetermined logical operation and the second predetermined logical operation is a logical conjunction operation (with the Or gates). (For Example: Par. 34-40 and 47-52)
Regarding Claim 4, Miller teaches (Figures 1-6) wherein a duty cycle of the duty cycle control signal is proportional to the duty cycle of the output signal (Fig. 4 buck pulses the combination of q3 and q4 provides the control signal buck pulses). (For Example: Par. 34-40 and 47-52)
Regarding Claim 6, Miller teaches (Figures 1-6) wherein when the first signal is the inversion of the first control signal and the second signal is the inversion of the second control signal (the comp2outb and comp1out1 are inverter signal used by Circuits A and B), each of the first predetermined logical operation and the second predetermined logical operation includes a logical conjunction operation and an inverse operation (with the OR gates and the inverter changing the comp1out and comp2out signals). (For Example: Par. 34-40 and 47-52)
Regarding Claim 12, Miller teaches (Figures 1-6) wherein a phase difference between the first ramp signal and the second ramp signal is 180 degrees (Figure 4 and abstract).
Regarding Claim 13, Miller teaches (Figures 1-6) wherein when a voltage level of the first ramp signal is equal to a voltage level of the second ramp signal (intersection of ramp1 and ramp2), both the voltage level of the first ramp signal and the voltage level of the second ramp signal are greater than zero (see fig. 4). (For Example: Par. 34-40 and 47-52)
Regarding Claim 14, Miller teaches (Figures 1-6) wherein when the voltage level of the first ramp signal (ramp1) is equal (intersection) to the voltage level of the second ramp signal (ramp2), a value of the voltage level of the first ramp signal is equal to half a value of a maximum voltage level of the first ramp signal and a value of the voltage level of the second ramp signal is equal to half a value of a maximum voltage level of the second ramp signal (see fig. 4 because they are 180 degrees out of phase and have the same frequency and magnitudes.). (For Example: Par. 34-40 and 47-52)
Regarding Claim 15, Miller teaches (Figures 1-6) wherein the dual ramp generator (12) includes: a first ramp signal generating circuit (fig. 6, generating ramp1) configured to perform a first charging-discharging operation according to a second clock signal (rst1) and thereby generate the first ramp signal; and a second ramp signal generating circuit (Figure 6, generating ramp2) configured to perform a second charging-discharging operation according to a first clock signal (rst2) and thereby generate the second ramp signal, wherein a phase difference between the first clock signal and the second clock signal is 180 degrees (they are 180 out of phase to produce the ramps being 180 out of phase). (For Example: Par. 34-40 and 47-52)
Regarding Claim 16, Miller teaches (Figures 1-6) wherein a duration of the first clock signal (rst2) having a first high voltage level within a first clock period is equal to a time for the second ramp signal changing from a maximum voltage level of the second ramp signal to a minimum voltage level of the second ramp signal (discharging of the capacitor 86 controlled by the switch 98), and a duration of the second clock signal (rst1) having a second high voltage level within a second clock period is equal to a time for the first ramp signal changing from a maximum voltage level of the first ramp signal to a minimum voltage level of the first ramp signal(discharging of the capacitor 82 controlled by the switch 92). (For Example: Par. 34-40 and 47-52)
Regarding Claim 20, Miller teaches (Figures 1-6) further comprising: an error amplifier (18) configured to generate the feedback signal according to the output signal and a reference signal (Vref). (For Example: Par. 22-23)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miller in view of Liu US 2023/0396162.
Regarding Claim 5, Miller teaches (Figures 1-6) an OR gate (64) configured to generate the duty cycle control signal (from 64) according to the first logical signal and the second logical signal (OR gates inputs).
Miller does not teach wherein the logical circuit includes: a first AND gate configured to generate a first logical signal according to the first control signal and the first conduction-control signal; a second AND gate configured to generate a second logical signal according to the second control signal and the second conduction-control signal.
Liu teaches (Figure 7) wherein the logical circuit (2015) includes: a first AND gate (2152a) configured to generate a first logical signal (2152a output) according to the first control signal and the first conduction-control signal (gate inputs); a second AND gate (20152b) configured to generate a second logical signal (gate output) according to the second control signal and the second conduction-control signal (gate input). (For Example: Par. 64-69)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Miller to include wherein the logical circuit includes: a first AND gate configured to generate a first logical signal according to the first control signal and the first conduction-control signal; a second AND gate configured to generate a second logical signal according to the second control signal and the second conduction-control signal, as taught by Liu to provide a circuitry with a relatively lower voltage stress and a relatively smaller ripple current.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miller in view of Choi US 20210119465.
Regarding Claim 7, Miller teaches (Figures 1-6) the circuit.
Miller does not teach wherein a duty cycle of the duty cycle control signal is inversely proportional to the duty cycle of the output signal.
Choi teaches (Figure 8) wherein a duty cycle of the duty cycle control signal is inversely proportional to the duty cycle of the output signal (the signal sent to the mux is inverter by the G3 signal inverter). (For Example: Par. 142)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Miller to include wherein a duty cycle of the duty cycle control signal is inversely proportional to the duty cycle of the output signal, as taught by Choi to reduce space for mounting components inside the electronic device, and a cost of the electronic device may increase due to additional components.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miller in view of Mangudi US 10554124.
Regarding Claim 9, Miller teaches (Figures 1-6) wherein the first signal is the first control signal and the second signal is the second control signal.
Miller does not teach when a voltage level of the first ramp signal is lower than a voltage level of the feedback signal, a voltage level of the first control signal is high; when the voltage level of the first ramp signal is higher than the voltage level of the feedback signal, the voltage level of the first control signal is low; when a voltage level of the second ramp signal is lower than the voltage level of the feedback signal, a voltage level of the second control signal is high; and when the voltage level of the second ramp signal is higher than the voltage level of the feedback signal, the voltage level of the second control signal is low.
Mangudi teaches (Figure 4) when a voltage level of the first ramp signal (1st ramp) is lower than a voltage level of the feedback signal (Error), a voltage level of the first control signal is high (D1, t4); when the voltage level of the first ramp signal is higher than the voltage level of the feedback signal, the voltage level of the first control signal is low (D1, t1); when a voltage level of the second ramp signa (2nd ramp)l is lower than the voltage level of the feedback signal (error), a voltage level of the second control signal is high (D2, t2); and when the voltage level of the second ramp signal is higher than the voltage level of the feedback signal, the voltage level of the second control signal is low (D2, t3). (For Example: Col. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Miller to include when a voltage level of the first ramp signal is lower than a voltage level of the feedback signal, a voltage level of the first control signal is high; when the voltage level of the first ramp signal is higher than the voltage level of the feedback signal, the voltage level of the first control signal is low; when a voltage level of the second ramp signal is lower than the voltage level of the feedback signal, a voltage level of the second control signal is high; and when the voltage level of the second ramp signal is higher than the voltage level of the feedback signal, the voltage level of the second control signal is low, as taught by Mangudi to avoid that the converter falls out of regulation due to inability to achieve a desired duty cycle.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miller in view of Faingersh US 20150256060.
Regarding Claim 17, Miller teaches (Figures 1-6) wherein: the first ramp signal generating circuit (generating ramp1) includes: a first current source (81); a first capacitor (82); a first switch first NMOS transistor configured to be turned on or turned off according to the second clock signal (rst1) and thereby allow the first current source to charge or discharge the first capacitor (82); and the second ramp signal generating circuit (generating ramp2) includes: a second current source (84); a second capacitor (86); a second switch configured to be turned on or turned off according to the first clock signal (rst2) and thereby allow the second current source to charge or discharge the second capacitor (86). (For Example: Par. 34-40 and 47-52)
Miller does not teach a first switch first NMOS transistor; and a first PMOS transistor configured to be turned on or turned off according to a voltage of the first capacitor and thereby determine the first ramp signal at a source terminal of the first PMOS transistor; a second NMOS transistor; and a second PMOS transistor configured to be turned on or turned off according to a voltage of the second capacitor and thereby determine the second ramp signal at a source terminal of the second PMOS transistor.
Faingersh teaches (Figures 1-2) a dual ramp generator (Fig. 1, 120 producing VINeff to 110-1 and 110-2), a first switch first NMOS transistor (Figure 2, 126a); and a first PMOS transistor (124a) configured to be turned on or turned off according to a voltage of the first capacitor (122a) and thereby determine the first ramp signal at a source terminal of the first PMOS transistor (at 124a); a second NMOS transistor (fig. 1, second soft start circuit of 120, 126); and a second PMOS transistor (fig. 2, 124) configured to be turned on or turned off according to a voltage of the second capacitor (122) and thereby determine the second ramp signal at a source terminal of the second PMOS transistor (124). (For Example: Par. 34-40)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Miller to include a first switch first NMOS transistor; and a first PMOS transistor configured to be turned on or turned off according to a voltage of the first capacitor and thereby determine the first ramp signal at a source terminal of the first PMOS transistor; a second NMOS transistor; and a second PMOS transistor configured to be turned on or turned off according to a voltage of the second capacitor and thereby determine the second ramp signal at a source terminal of the second PMOS transistor, as taught by Faingersh to avoid restarting ramp signal which would create a conflict in that it would disrupt the operation of the converter, which could cause system failure.
Allowable Subject Matter
Claims 8, 10-11 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 8; prior art of record fails to disclose either by itself or in combination: “…the logical circuit includes: a first AND gate configured to generate a first logical signal according to an inversion signal of the first control signal and the first conduction-control signal; a second AND gate configured to generate a second logical signal according to an inversion signal of the second control signal and the second conduction-control signal; and a NOR gate configured to generate the duty cycle control signal according to the first logical signal and the second logical signal”
Claim 10; prior art of record fails to disclose either by itself or in combination: “…wherein the first signal is the inversion of the first control signal and the second signal is the inversion of the second control signal; when a voltage level of the first ramp signal is lower than a voltage level of the feedback signal, a voltage level of the first control signal is low; when the voltage level of the first ramp signal is higher than the voltage level of the feedback signal, the voltage level of the first control signal is high; when a voltage level of the second ramp signal is lower than the voltage level of the feedback signal, a voltage level of the second control signal is low; and when the voltage level of the second ramp signal is higher than the voltage level of the feedback signal, the voltage level of the second control signal is high.
Claim 11; prior art of record fails to disclose either by itself or in combination: “…wherein at least one of the first comparator and the second comparator has an output delay due to a comparison operation; when a voltage level of the duty cycle control signal is high and a high-level duration of the duty cycle control signal is proportional to the duty cycle of the output signal, the high-level duration is shorter than the output delay; and when the voltage level of the duty cycle control signal is low and a low-level duration of the duty cycle control signal is proportional to the duty cycle of the output signal, the low-level duration is shorter than the output delay.”
Claim 18; prior art of record fails to disclose either by itself or in combination: “…wherein the dual ramp generator further includes: a clock generating circuit, comprising: a first comparing circuit configured to compare a first half-cycle ramp signal with a reference signal to generate a first comparison result; a second comparing circuit configured to compare a second half-cycle ramp signal with the reference signal to generate a second comparison result; an SR latch configured to generate a first initial pulse signal according to the first comparison result and generate a second initial pulse signal according to the second comparison result, wherein the first initial pulse signal is an inversion signal of the second initial pulse signal; a delay adjusting circuit configured to delay a high-to-low voltage level transition of the first initial pulse signal according to predetermined delay setting to generate a first pulse signal, and further configured to delay a high-to-low voltage level transition of the second initial pulse signal according to the predetermined delay setting to generate a second pulse signal; and an AND-gate circuit configured to generate the first clock signal according to the first initial pulse signal and the second pulse signal, and further configured to generate the second clock signal according to the second initial pulse signal and the first pulse signal.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838