Prosecution Insights
Last updated: April 19, 2026
Application No. 18/601,419

TIME DELAY INTEGRATION SENSOR WITH INCREASED APERTURE AREA

Non-Final OA §102§103§DP
Filed
Mar 11, 2024
Examiner
MONK, MARK T
Art Unit
2637
Tech Center
2600 — Communications
Assignee
Taiwan Space Agency
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
446 granted / 588 resolved
+13.9% vs TC avg
Strong +20% interview lift
Without
With
+20.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
15 currently pending
Career history
603
Total Applications
across all art units

Statute-Specific Performance

§101
4.1%
-35.9% vs TC avg
§103
54.0%
+14.0% vs TC avg
§102
20.3%
-19.7% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 588 resolved cases

Office Action

§102 §103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 2, 4, 5, and 7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14, 15, and 17 - 19 of U.S. Patent No. 11,336,843, Liu et al. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in this application are broader than in Liu et al 11,336,843. Regarding claim 1 Liu et al 11,336,843 discloses of applicant’s A time delay integration (TDI) complementary metal-oxide-semiconductor (CMOS) image sensor, configured to capture an image frame using a rolling shutter and move with respect to a scene in an along-track direction, the image sensor comprising: a pixel array, comprising multiple pixel columns, each of the pixel columns comprising multiple pixels arranged in the along-track direction, and one pixel of each pixel group of the multiple pixels having an extension in the along-track direction to compensate a line time difference of using the rolling shutter, wherein each pixel group has a first pixel and a second pixel (claim 14, A TDI CMOS image sensor, configured to capture an image frame using a rolling shutter and move with respect to a scene in an along-track direction, the image sensor comprising: a pixel array, comprising multiple pixel columns, each of the pixel columns comprising multiple pixels arranged in the along-track direction, and two adjacent pixel groups of the pixels having a separation (extension) space therebetween to compensate a line time difference of using the rolling shutter, wherein each pixel group has a first pixel and a second pixel). Regarding claim 2 Liu et al 11,336,843 discloses of applicant’s wherein the image sensor further comprises: a first readout circuit, coupled to the first pixel of the pixel group in the pixel columns, and configured to read pixel data of the first pixel; and a second readout circuit, coupled to the second pixel of the pixel group in the pixel columns, and configured to read pixel data of the second pixel (claim 15, wherein the image sensor further comprises: a first readout circuit, coupled to the first pixel of the pixel group in the pixel columns, and configured to read pixel data of the first pixel; and a second readout circuit, coupled to the second pixel of the pixel group in the pixel columns, and configured to read pixel data of the second pixel). Regarding claim 4 Liu et al 11,336,843 discloses of applicant’s wherein the first pixel and the second pixel are exposed simultaneously, and pixel data of the first pixel and the second pixel are integrated simultaneously by the first readout circuit and the second readout circuit (claim 17, wherein the first pixel and the second pixel are exposed simultaneously, and pixel data of the first pixel and the second pixel are integrated simultaneously by the first readout circuit and the second readout circuit). Regarding claim 5 Liu et al 11,336,843 discloses of applicant’s wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is read by the first readout circuit, and the pixel data in the second image frame corresponding to the same position of the scene is read by the second readout circuit (claim 18, wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is read by the first readout circuit, and the pixel data in the second image frame corresponding to the same position of the scene is read by the second readout circuit). Regarding claim 7 Liu et al 11,336,843 discloses of applicant’s wherein the line time difference is a time interval between a time of starting exposure of two adjacent pixel rows (claim 19, wherein the line time difference is a time interval between a time of starting exposure of two adjacent pixel rows). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 - 8 is/are rejected under 35 U.S.C. 102b as being anticipated by Liu et al US Publication No. 2021/0409630. Regarding claim 1 Liu et al 2021/0409630 discloses of Fig. 1 – 9C of applicant’s a time delay integration (TDI) complementary metal-oxide-semiconductor (CMOS) image sensor, configured to capture an image frame using a rolling shutter and move with respect to a scene in an along-track direction (paragraph 0055, Fig. 5, the TDI CMOS image sensor 500 captures an image frame using a rolling shutter, and moves toward an along-track direction Da_t with respect to a scene); the image sensor comprising: a pixel array, comprising multiple pixel columns, each of the pixel columns comprising multiple pixels arranged in the along-track direction, and one pixel of each pixel group of the multiple pixels having an extension in the along-track direction to compensate a line time difference of using the rolling shutter, wherein each pixel group has a first pixel and a second pixel (paragraph 0055 – 0056 the TDI CMOS image sensor 500 includes a pixel array 51 which includes multiple pixel columns 512 each including multiple pixels arranged in the along-track direction Da_t. A separation space 5124 is arranged between two adjacent pixel groups to compensate a line time difference in using the rolling shutter, wherein each pixel group includes a first pixel 5123 and a second pixel 5215 directly connected to each other such that the image sensor 500 comprising: a pixel array 51, comprising multiple pixel columns 512, each of the pixel columns 512 comprising multiple pixels 5123 and 5125, in a pixel group, arranged in the along-track column direction, and one pixel 5125 of each pixel group of the multiple pixels having an extension separation space 5124, at the bottom of pixel 5125, in the along-track column direction to compensate a line time difference of using the rolling shutter, wherein each pixel group has a first pixel 5123 and a second pixel 5125). Regarding claim 2 Liu et al 2021/0409630 further discloses of applicant’s wherein the image sensor further comprises: a first readout circuit, coupled to the first pixel of the pixel group in the pixel columns, and configured to read pixel data of the first pixel; and a second readout circuit, coupled to the second pixel of the pixel group in the pixel columns, and configured to read pixel data of the second pixel (paragraph 0057 the TDI CMOS image sensor 500 further includes a first readout circuit 53 and a second readout circuit 55. As shown in FIG. 5, the first readout circuit 53 is coupled to multiple first pixels 5123 in the pixel columns 512 via a readout line 513 so as to read pixel data of the first pixels 5123, and the second readout circuit 55 is coupled to multiple second pixels 5125 in the pixel columns 512 via a readout line 515 so as to read pixel data of the second pixels 5125). Regarding claim 3 Liu et al 2021/0409630 further discloses of applicant’s wherein the first pixel and the second pixel are directly adjacent to each other in the along-track direction, and adjacent pixel groups in the same pixel column are directly adjacent to each other in the along-track direction (paragraph 0056, Fig. 5, the TDI CMOS image sensor 500 includes a pixel array 51. The pixel array 51 includes multiple pixel columns 512 each including multiple pixels arranged in the along-track direction Da--_t. A separation space 5124 is arranged between two adjacent pixel groups to compensate a line time difference in using the rolling shutter, wherein each pixel group includes a first pixel 5123 and a second pixel 5125 directly connected to each other such that the first pixel 5123 and the second pixel 5125 are directly adjacent to each other in the along-track column direction, and adjacent pixel groups in the same pixel column are directly adjacent to each other in the along-track column direction as seen in Fig. 5). Regarding claim 4 Liu et al 2021/0409630 further discloses of applicant’s wherein the first pixel and the second pixel are exposed simultaneously, and pixel data of the first pixel and the second pixel are integrated simultaneously by the first readout circuit and the second readout circuit (paragraph 0062 the first pixel 5123 and the second pixel 5125 of each pixel group are exposed simultaneously, and the pixel data thereof is respectively integrated by the first readout circuit 53 and the second readout circuit 55 simultaneously). Regarding claim 5 Liu et al 2021/0409630 further discloses of applicant’s wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is read by the first readout circuit, and the pixel data in the second image frame corresponding to the same position of the scene is read by the second readout circuit (paragraph 0062 – 0064 in the line time of F1_2 of a first image frame (e.g., frame including F1_1 to F1_4), Stage3 and Stage4 are exposed at the same time, and pixel data of Stage3 (e.g., ID) is integrated by the first readout circuit 53 to the integrator 63, and pixel data of Stage4 (e.g., IC) is integrated by the second readout circuit 55 to the integrator 64. In the line time of F1_3 of the first image frame, Stage5 and Stage6 are exposed at the same time, and pixel data of Stage5 (e.g., IB) is integrated by the first readout circuit 53 to the integrator 65, and pixel data of Stage6 (e.g., IA) is integrated by the second readout circuit 55 to the integrator 66. The exposure and integration of other line times in a frame period T of the first image frame are similar to the line times F1_2 and F1_3. In the line time of F2_3 of a second image frame (e.g., frame including F2_1 to F2_4), Stage5 and Stage6 are exposed at the same time, and pixel data of Stage5 (e.g., IC) is integrated by the first readout circuit 53 to the integrator 64, shown as 2IC indicating integrated by two times; and pixel data of Stage6 (e.g., IB) is integrated by the second readout circuit 55 to the integrator 65, shown as 2IB indicating integrated by two times. The exposure and integration of other line times in a frame period T of the second image frame are similar to the line times F2_3 such that the image sensor 500 further comprises multiple integrators 63 and 64 configured to respectively store pixel data in a first image frame including F1_1 to F1_4 and a second image frame including F2_1 to F2_4, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame including F1_1 to F1_4 corresponding to the same position of the scene is read by the first readout circuit 53, and the pixel data in the second image frame including F2_1 to F2_4 corresponding to the same position of the scene is read by the second readout circuit 55). Regarding claim 6 of applicant’s wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is detected by the first pixel, and the pixel data in the second image frame corresponding to the same position of the scene is detected by the second pixel. Claim 6 is rejected for the reasons found in rejected claim 5 above. Regarding claim 7 Liu et al 2021/0409630 further discloses of applicant’s wherein the line time difference is a time interval between a time of starting exposure of two adjacent pixel rows (paragraph 0035 the line time difference t is a time interval between a time of starting or ending exposure of two adjacent pixel rows). Regarding claim 8 Liu et al 2021/0409630 further discloses of applicant’s wherein the extension is a multiplication of a pixel height of pixels without the extension in the along-track direction by a time ratio of the line time difference of the rolling shutter and a frame period of capturing the image frame (paragraph 0058 the extension separation space 5124 is a multiplication of a pixel height W in the along-track direction Da_t by a time ratio of a line time difference t of the rolling shutter and a frame period T of capturing the image frame like in FIG. 6 showing two image frames). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 10 – 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al US Publication No. 2021/0409630 in view of Ohkawa US Publication No. 2009/0321800. Regarding claim 10, claim 10 is rejected for being fully encompassed by the reasons found in rejected claim 1 above and where Liu et al teaches imager structure where pixel areas are the same in the column direction but does not expressively disclose a first aperture area of a first pixel of each pixel group of the multiple pixels is longer than a second aperture area of a second pixel of the each pixel group by an extension in the along-track direction, Ohkawa teaches an imager structure where the green pixel areas are longed in the column direction than the red and blue pixel areas in the column direction. Ohkawa teaches of Fig. 1 – 16 of applicant’s a first aperture area of a first pixel of each pixel group of the multiple pixels is longer than a second aperture area of a second pixel of the each pixel group by an extension in the along-track direction (paragraph 0069, Fig. 2, the green photodiode PDG has a broader area than the area of each of the red photodiode PDR and blue photodiode PDB as seen in Fig. 2 in the column direction where the green photodiode PDG has a broader area by being longer than the length of the area of each of the red photodiode PDR and blue photodiode PDB such that a first aperture area of a first green photodiode PDB pixel of each pixel group of green and red pixels and group of green and blue pixels of the multiple pixels is longer than a second aperture area of a second red photodiode PDR or blue photodiode PDB pixel of the each pixel group by an extension in the along-track column direction). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Liu et al in a manner similar to Ohkawa et al. Doing so would result improving Liu et al invention in a similar way as Ohkawa et al – namely the ability to provide an imager structure where the green pixel areas are longed in the column direction than the red and blue pixel areas in the column direction, in Ohkawa et al invention, to the imager structure where pixel areas are the same in the column direction in Liu et al invention. Regarding claim 11 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the image sensor further comprises: a first readout circuit, coupled to the first pixel of the pixel group in the pixel columns, and configured to read pixel data of the first pixel; and a second readout circuit, coupled to the second pixel of the pixel group in the pixel columns, and configured to read pixel data of the second pixel. Claim 11 is rejected for the reasons found in rejected claims 2 and 10 above. Regarding claim 12 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the first pixel and the second pixel are directly adjacent to each other in the along-track direction, and adjacent pixel groups in the same pixel column are directly adjacent to each other in the along-track direction. Claim 12 is rejected for the reasons found in rejected claims 3 and 11 above. Regarding claim 13 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the first pixel and the second pixel are exposed simultaneously, and pixel data of the first pixel and the second pixel are integrated simultaneously by the first readout circuit and the second readout circuit. Claim 13 is rejected for the reasons found in rejected claims 4 and 11 above. Regarding claim 14 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is read by the first readout circuit, and the pixel data in the second image frame corresponding to the same position of the scene is read by the second readout circuit. Claim 14 is rejected for the reasons found in rejected claims 5 and 11 above. Regarding claim 15 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the image sensor further comprises multiple integrators configured to respectively store pixel data in a first image frame and a second image frame, adjacent to each other, corresponding to a same position of the scene, wherein the pixel data in the first image frame corresponding to the same position of the scene is detected by the first pixel, and the pixel data in the second image frame corresponding to the same position of the scene is detected by the second pixel. Claim 15 is rejected for the reasons found in rejected claims 6 and 11 above. Regarding claim 16 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the line time difference is a time interval between a time of starting exposure of two adjacent pixel rows. Claim 16 is rejected for the reasons found in rejected claims 7 and 10 above. Regarding claim 17 of the combination of Liu et al 2021/0409630 in view of Ohkawa, Liu et al 2021/0409630 discloses of applicant’s wherein the extension is a multiplication of a pixel height of pixels without the extension in the along-track direction by a time ratio of the line time difference of the rolling shutter and a frame period of capturing the image frame. Claim 17 is rejected for the reasons found in rejected claims 8 and 10 above. Regarding claim 19, claim 19 is rejected for being fully encompassed by the reasons found in rejected claim 1, 2, and 10 above. Allowable Subject Matter Claims 9, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK T MONK whose telephone number is (571)270-7454. The examiner can normally be reached Monday thru Friday 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARK T MONK/Primary Examiner, Art Unit 2637
Read full office action

Prosecution Timeline

Mar 11, 2024
Application Filed
Jan 20, 2026
Non-Final Rejection — §102, §103, §DP
Apr 01, 2026
Examiner Interview Summary
Apr 01, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
96%
With Interview (+20.2%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 588 resolved cases by this examiner. Grant probability derived from career allow rate.

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