DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 6/8/2026 has been carefully reconsidered by the examiner. As a result, the examiner agrees with applicant’s arguments. However, there is still an outstanding issue have not been resolved yet. Therefore, the application cannot be in condition for allowance yet until a terminal disclaimer is filed to overcome the non-statutory double patenting rejections made in the previous office action dated 3/6/2026.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,958. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the USP 11,942,958 discloses similar limitations and functions of the claim 1 of the instant application, such as, a plurality of circuit elements configured in a rectangular area of a substrate; and a set of switches configured to selectively connect the circuit elements to an output node; wherein the device is configured to operate the set of switches to connect subsets of the circuit elements to the output node in a pattern that reduces deviation from a linear output in the output node for more than one scenario of directional variability in manufacture of the circuit elements. Although the claim 1 of the USP 11,942,958 fails to discloses switches in the claim. However, in order to connect electric component to the output node, switches are needed to perform the connecting function. In addition, claim 1 of USP 11,942,958 used the term “electric component” which is similar meaning to “circuit elements” as claimed in the claim 1 of the instant application.
Claim 2 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,958. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the USP 11,942,958 discloses similar limitations and functions of the claim 1 of the instant application, such as, wherein the set of switches are configured on the substrate. Although the claim 1 of the USP 11,942,958 fails to discloses switches in the claim. However, in order to connect electric component to the output node, switches are needed to perform the connecting function.
Claim 10 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,958. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the USP 11,942,958 discloses similar limitations and functions of the claim 1 of the instant application, such as, a plurality of circuit elements configured in a rectangular area of a substrate; and a set of switches configured to selectively connect the circuit elements to an output node; wherein the device is configured to operate the set of switches to connect subsets of the circuit elements to the output node in a pattern that reduces deviation between: a first output in the output node when the circuit elements have no variability in manufacture; and a second output in the output node when the circuit elements have directional variability in manufacture in any of a plurality of directions. Although the claim 1 of the USP 11,942,958 fails to discloses switches in the claim. However, in order to connect electric component to the output node, switches are needed to perform the connecting function. In addition, claim 1 of USP 11,942,958 used the term “electric component” which is similar meaning to “circuit elements” as claimed in the claim 1 of the instant application.
Claim 11 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,958. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the USP 11,942,958 discloses similar limitations and functions of the claim 1 of the instant application, such as, wherein the set of switches are configured on the substrate. In addition, claim 1 of USP 11,942,958 used the term “electric component” which is similar meaning to “circuit elements” as claimed in the claim 1 of the instant application.
Claim 17 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,958. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the USP 11,942,958 discloses similar limitations and functions of the claim 1 of the instant application, such as, providing a plurality of circuit elements in a rectangular area of a substrate; providing, on the substrate, a set of switches to selectively connect the circuit elements to an output node; operating the set of switches to connect subsets of the circuit elements to the output node in a pattern that reduces deviation between: a first output in the output node when the circuit elements have no variability in manufacture; and a second output in the output node when the circuit elements have directional variability in manufacture in any of a plurality of directions. Although the claim 1 of the USP 11,942,958 fails to discloses switches in the claim. However, in order to connect electric component to the output node, switches are needed to perform the connecting function. In addition, claim 1 of USP 11,942,958 used the term “electric component” which is similar meaning to “circuit elements” as claimed in the claim 1 of the instant application.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements are connected to the output node to provide output; and each respective circuit element in the plurality of circuit elements is configured to be selectively connected, via one of the switches, between an input and the output node.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements and the set of switches are configured between two input nodes to provide the output that varies based on connections provided by the switches.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements include first circuit elements and second circuit elements; wherein the first circuit elements are selectively connectable by the set of switches to a first node among the two input nodes; and wherein the second circuit elements are selectively connectable by the set of switches to a second node among the two input nodes.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein in absence of variability in manufacture of the plurality of circuit elements, the output is a function of a count of the first circuit elements connected between the first node and the output node, and a count of the second circuit elements connected between to the second node and the output node.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each of the plurality of circuit elements is a resistor.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each of the plurality of circuit elements is a capacitor.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each of the plurality of circuit elements is an inductor.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each respective circuit element in the plurality of circuit elements is configured to be selectively connected, via one of the switches, between an input and the output node.
Claim 13 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements and the set of switches are configured between two input nodes to provide the second output that varies based on connections provided by the switches.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements include first circuit elements and second circuit elements; wherein the first circuit elements are selectively connectable by the set of switches to a first node among the two input nodes; and wherein the second circuit elements are selectively connectable by the set of switches to a second node among the two input nodes.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the first output is a function of a count of the first circuit elements connected between the first node and the output node, and a count of the second circuit elements connected between to the second node and the output node.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each of the plurality of circuit elements is a resistor, a capacitor, or an inductor.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein each respective circuit element in the plurality of circuit elements is configured to be selectively connected, via one of the switches, between an input and the output node.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements and the set of switches are configured between two input nodes to provide the second output that varies based on connections provided by the switches.
Claim 20 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, such as: wherein the plurality of circuit elements include first circuit elements and second circuit elements; wherein the first circuit elements are selectively connectable by the set of switches to a first node among the two input nodes; wherein the second circuit elements are selectively connectable by the set of switches to a second node among the two input nodes; wherein the first output is a function of a first count of the first circuit elements connected between the first node and the output node, and a second count of the second circuit elements connected between to the second node and the output node; and wherein the first output is independent of which of the first count of the first circuit elements is being selected for connection between the first node and the output node, and independent of which of the second count of the second circuit elements is being selected for connection between the second node and the output node.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM T MAI whose telephone number is (571)272-1807. The examiner can normally be reached Monday-Friday 6am-2pm eastern time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571 272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAM T MAI/Primary Examiner, Art Unit 2845
Prosecution Insights