DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 12, and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura (US 7,688,143).
In regard to Claim 1:
Kimura discloses, in Figure 8, an amplifying circuit, comprising:
a first amplifying circuit (M1, M2, M7) coupled between a high-voltage terminal (Vdd) and a low-voltage terminal (ground) and configured to output a first amplified signal (ISQ1) according to an input signal (Vc); and
a second amplifying circuit including:
an input-stage circuit (M5, M6) configured to receive the input signal (Vc) and accordingly output an input-stage output signal (ID1, ID2) to a set of intermediate node(s) (Icon1, Icon2 nodes);
a transconductance and loading circuit (M8-M13) coupled between the high-voltage terminal (Vdd) and the input-stage circuit (M5, M6), and configured to output a transconductance-enhancement signal to the set of intermediate node(s) (Icon1, Icon2 nodes) according to the first amplified signal (ISQ1, Column 8: lines 55-67, Column 9: lines 1-3); and
an output-stage circuit (11, 12) coupled between the high-voltage terminal (Vdd) and the low-voltage terminal (ground) and further coupled to the set of intermediate node(s) (Id1, Id2 nodes), and configured to output an output signal (Vout) according to the input-stage output signal (Id1, Id2) and the transconductance-enhancement signal (Icon1, Icon2).
In regard to Claim 2:
Kimura discloses, in Figure 8, the amplifying circuit of claim 1, wherein the first amplifying circuit includes:
a signal input circuit (M1, M2) including a set of input terminal(s) (M1, M2 gates) and a set of output terminal(s) (M1, M2 drains), the signal input circuit configured to receive the input signal (Vc) with the set of input terminal(s) (M1, M2 gates) and output the first amplified signal (ISQ1) with the set of output terminal(s) (M1, M2 drains); and
a diode-connected circuit (M7) coupled between the high-voltage terminal (Vdd) and the set of output terminal(s) (M1, M2 drains), and configured to determine a transconductance of the first amplifying circuit in conjunction with the signal input circuit (Column 9: lines 4-25).
In regard to Claim 3:
Kimura discloses, in Figure 8, The amplifying circuit of claim 2, wherein the diode-connected circuit (M7) and the transconductance and loading circuit (M8-M13) of the second amplifying circuit jointly function as a current mirror (M7 and M8 form a current mirror).
In regard to Claim 5:
Kimura discloses, in Figure 8, The amplifying circuit of claim 2, wherein the first amplifying circuit (M1, M2, M7) further includes: a bias circuit (I0) coupled between the signal input circuit (M1, M2) and the low-voltage terminal (ground), and configured to regulate a current from the signal input circuit to the low-voltage terminal (Column 9: lines 35-47).
In regard to Claim 12:
Kimura discloses, in Figure 8, The amplifying circuit of claim 1, wherein the second amplifying circuit (M5-M6, M8-M13) further includes: a bias circuit (I0) coupled between the input-stage circuit (M5, M6) and the low-voltage terminal (ground), and configured to regulate a current from the input-stage circuit to the low-voltage terminal (Column 9: lines 35-47).
In regard to Claim 14:
Kimura discloses, in Figure 8, The amplifying circuit of claim 1, further comprising: a cascode transistor (M3, M4) coupled between the high-voltage terminal (Vdd) and the first amplifying circuit (M1, M2, M7).
In regard to Claim 15:
Kimura discloses, in Figure 8, The amplifying circuit of claim 1, wherein the input signal (Vc) is an input differential signal composed of complementary input signals (Column 8: lines 45-54), and the output signal (Vout) is an output differential signal composed of complementary output signals (Column 9: lines 4-25).
Allowable Subject Matter
Claims 4, 6-11, 13, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ivanov et al. (US 2016/0006403) discloses multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit.
Cove (US 2004/0164807) discloses a circuit includes a limiting amplifier, the limiting amplifier including an output node. The circuit also includes an active inductor coupled to the output node, and may exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
Kimura (US 5,712,594) discloses an OTA capable of low-voltage operation at a voltage as low as approximately 1 V while restraining the circuit scale increase and keeping approximately the same input voltage range as that of the conventional one. This OTA has a differential pair of first and second bipolar or MOS transistors driven by a first constant current source, and a squarer driven by a second constant current source. The differential pair is applied with an input voltage and produces an output current of the OTA. The squarer is applied with the input voltage and produces differentially first and second output currents having a square-law characteristic.
Shen et al. (US 9,473,122) discloses a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance “gm” throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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