DETAILED ACTION
1. This action is in response to the application filed on 3/11/24.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. Applicant’s arguments with respect to claim(s) 1 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-2 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210408921) in view of Chen (US 20230188046).
Regarding claim 1: Yang et al. disclose (i.e. figures 1A, 1B, and 2- 10) a controller (i.e. 100) for a power converter (i.e. 1001), the controller comprising:
a first drive signal generator (i.e. generator for signal SH) configured to generate a first drive signal (i.e. SH) to turn off a first transistor (i.e. 30) at a first time (i.e. figure 3: SH long off time) and turn on the first transistor (i.e. 30) at a second time (i.e. figure 3: on time, after long off time), the first transistor (i.e. 30) being configured to receive an input voltage (i.e. Vin) and related to a primary winding (i.e. NP) coupled to an auxiliary winding (i.e. NA) and a secondary winding (i.e. NS), the secondary winding (i.e. NS) being related to an output voltage (i.e. Vo), the second time (i.e. figure 3: on time, after long off time) being later than the first time (i.e. figure 3: SH long off time);
a second drive signal generator (i.e. generator for signal SL) configured to: generate a second drive signal (i.e. SL) to turn on a second transistor (i.e. 40) at a third time (i.e. figure 3: SL, on time PRES), the second transistor (i.e. 40) being coupled to the first transistor (i.e. 30) and related to the primary winding (i.e. NP), the third time (i.e. figure3: SL, on time PRES) being later than the first time (i.e. figure 3: SH long off time) and being earlier than the second time (i.e. figure 3: on time, after long off time);
change the second drive signal (i.e. SL) to turn off the second transistor (i.e. 40) at a fourth time (i.e. figure 3: SL off time between TDLY), the fourth time (i.e. figure 3: SL off time between TDLY) being later than the third time (i.e. figure3: SL, on time PRES) and being earlier than the second time (i.e. figure 3: on time, after long off time); and
change the second drive signal (i.e. SL) to turn on the second transistor (i.e. 40) at a fifth time (i.e. figure 3: SL on time PSSW), the fifth time (i.e. figure 3: SL on time PSSW) being later than the fourth time (i.e. figure 3: SL off time between TDLY) and being earlier than the second time (i.e. figure 3: on time, after long off time);
a first controller (i.e. first controller portion of 100) configured to generate a first control signal (i.e. S1) based at least in part on a first voltage (i.e. VNA) related to the auxiliary winding (i.e. NA) and output the first control signal (i.e. S1) to the second drive signal generator (i.e. 103); wherein the second drive signal generator (i.e. 103) is further configured to:
in response to the first control signal (i.e. S1) changing from a first logic level (i.e. on/off) to a second logic level (i.e. on/off), change the second drive signal (i.e. SL) to turn off the second transistor (i.e. 40) at a sixth time (i.e. figure 3: SL turn off between TRH), the sixth time (i.e. figure 3: SL turn off between TRH) being later than the fifth time (i.e. figure 3: SL on time PSSW) and being earlier than the second time (i.e. figure 3: on time, after long off time) (i.e. ¶ 34-47),
but does not specifically disclose the first controller includes: a ramp signal generator configured to generate a ramp signal; and a comparator configured to receive the ramp signal and a compensation signal related to the first voltage and generate the first control signal based at least in part on the compensation signal and the ramp signal.
Chen discloses a power supply (i.e. figures 1-3) comprising the first controller includes: a ramp signal generator (i.e. 202) configured to generate a ramp signal (i.e. from 202); and a comparator (i.e. 204) configured to receive the ramp signal (i.e. from 202) and a compensation signal (i.e. Vcomp) related to the first voltage (i.e. VCC) and generate the first control signal (i.e. from CMP2) based at least in part on the compensation signal (i.e. Vcomp) and the ramp signal (i.e. from 202).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Yang’s invention with the power supply as disclose by Chen, because it is desired to further implement soft switching technique for improving the converter efficiency with a high switching frequency.
Regarding claim 2: Yang discloses (i.e. figures 1A, 1B, and 2- 10) wherein: the first logic level is a logic low level (i.e. S1 off); and the second logic level is a logic high level (i.e. S1 on).
Regarding claim 24: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated).
Allowable Subject Matter
6. Claims 16-23 and 25 are allowed.
The following is an examiner’s statement of reasons for allowance: In regards to claims 16 and 25, the prior art fails to disclose an enablement controller configured to generate an enablement control signal based at least in part on a first voltage related to the auxiliary winding and output the enablement control signal to the second drive signal generator; and a first controller configured to generate a first control signal based at least in part on a second voltage related to the output voltage and output the first control signal to the second drive signal generator: wherein the second drive signal generator is further configured to: in response to the first control signal changing from a first logic level to a second logic level when the enablement control signal is at a third logic level, change the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; and in response to the first control signal changing from the first logic level to the second logic level when the enablement control signal is at a fourth logic level, not change the second drive signal so that the second transistor remains being turned off from the fourth time to the second time; wherein: the first logic level and the second logic level are different; and the third logic level and the fourth logic level are different.
7. Claims 3-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838