Prosecution Insights
Last updated: April 19, 2026
Application No. 18/601,586

UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM

Final Rejection §103
Filed
Mar 11, 2024
Examiner
HARRINGTON, CHERI L.
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
96%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
210 granted / 307 resolved
+13.4% vs TC avg
Strong +27% interview lift
Without
With
+27.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
26 currently pending
Career history
333
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
25.0%
-15.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 307 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-6 and 8-19 are pending. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-6, 8, 11-14, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tidwell et al. (US 20180335978) in view of Thomas et al. (US 20160147280). Regarding claim 1, Tidwell teaches A system comprising: a memory device; and (Fig. 1 (memory channels – 160) which is a subsystem of the storage device) a processing device (Fig. 1 (storage controller – 128)), operatively coupled with the memory device, to perform operations comprising: ([0055], “each memory channel 160 coupled to storage controller 128”) identifying a temperature value associated with the memory device; ([0069], “power usage monitor 124 is coupled to and provides board power measurement(s) and/or temperature measurements to storage controller 128. … the subsystem for which power and/or temperature is monitored includes all the memory channels of storage device 120”) determining a power limit for the memory device based on the temperature value; (Fig. 4, (412), [0100], “When the power/temperature measurement(s) exceed the predefined threshold(s), this indicates that the storage device is using more power, on average, than allowed, and therefore the total power credits available is reduced.” And [0103], “[0103], “the total number of average power credits available to be allocated is adjusted, based on power usage measurements and/or temperature measurements for storage device 120 or a subsystem of storage device 120 (e.g., temperature measurements by power usage monitor 124), when those measurements indicate that the temperature of the storage device, or a subsystem of the storage device, is above a threshold temperature or is in danger of rising above the threshold temperature” where the number of credits allocated to the memory channel is the power limit of the subsystem (i.e. the memory channel)) determining a current power usage level of the memory device; and ([0100], “When the power/temperature measurement(s) exceed the predefined threshold(s), this indicates that the storage device is using more power, on average, than allowed, and therefore the total power credits available is reduced.” And [0103], “the total number of average power credits available to be allocated is adjusted, based on power usage measurements and/or temperature measurements for storage device 120 or a subsystem of storage device 120 (e.g., temperature measurements by power usage monitor 124), when those measurements indicate that the temperature of the storage device, or a subsystem of the storage device, is above a threshold temperature or is in danger of rising above the threshold temperature”) responsive to determining that the current power usage level of the memory device does not satisfy the power limit, determining to enter a power-limited mode for the memory device. (Fig. 4, (420, 426, 428), [0103], “the total number of average power credits available to be allocated is adjusted, based on power usage measurements and/or temperature measurements for storage device 120 or a subsystem of storage device 120 (e.g., temperature measurements by power usage monitor 124), when those measurements indicate that the temperature of the storage device, or a subsystem of the storage device, is above a threshold temperature or is in danger of rising above the threshold temperature … in some embodiments, “temperature throttling” is accomplished by reducing the total number of power credits to be allocated (in embodiments using a single type of power credit) or reducing the number of average power credits to be allocated (in embodiments using two or more types of power credits) when the temperature of the storage device is above a threshold temperature.” And [0100], “Reducing the total power credits available will result in fewer commands being executed per unit of time (sometimes called epochs), which will reduce the total or average power used by the storage device, which, in turn, will reduce the temperature of the storage device or the portion of the storage device monitored by power usage monitor 124.”) Tidwell teaches controlling memory devices power consumption with thresholds but does not specifically teach using set of power consumption thresholds related to temperature ranges. Thomas teaches identifying a set of power consumption thresholds for the memory device, wherein each power consumption threshold in the set of power consumption thresholds corresponds to a respective range of temperature values of a plurality of ranges of temperature values: (Figs. 16-18, [0122], “ at block 1710 by determining a processor temperature, as discussed above. Next at block 1720 the temperature can be mapped to a temperature range bucket. Next a dynamic power limit value may be obtained from a table using the determined temperature range bucket (block 1730). Note here, the table may be configured to include entries each having a different power limit associated with a given temperature range and an index field, which is used to access the given entry based on the temperature range bucket.”) selecting, based on the temperature value associated with the memory device, a power consumption threshold of the set of power consumption thresholds for the memory device (Figs. 16-18, [0122], “ at block 1710 by determining a processor temperature, as discussed above. Next at block 1720 the temperature can be mapped to a temperature range bucket. Next a dynamic power limit value may be obtained from a table using the determined temperature range bucket (block 1730). Note here, the table may be configured to include entries each having a different power limit associated with a given temperature range and an index field, which is used to access the given entry based on the temperature range bucket.” [0126], “an updated power limit may be determined based on the temperature.”) comparing the current power usage level to the power consumption threshold: ([0123], “Next, a determination may be made as to whether operation of the processor is within this determined the power budget (diamond 1760).”) responsive to determining, based on the comparison, that the current power usage level of the memory device exceeds the power consumption threshold, determining to enter a power-limited mode for the memory device. ([0123], “ next a power budget may be determined using this obtained power limit (block 1750), e.g., as discussed above regarding Equation 2. Next, a determination may be made as to whether operation of the processor is within this determined the power budget (diamond 1760). … if it is determined that the processor is not operating within the determined power budget, control passes to block 1780, where one or more operating parameters may be appropriately reduced to enable the processor to operate at a power level within the power budget.”) Tidwell and Thomas are analogous art. Thomas is cited to teach a similar concept of power management in an electronic device using power limits/budgets. Thomas teaches using temperature values and ranges to determine power limits of the system (processor/memory). Tidwell teaches power management of memories using a power limit threshold. Tidwell does not specifically teach using temperature ranges and temperature values to dynamically adjust the power limits. Based on Thomas, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Tidwell to use temperature ranges to provide adjustments to the power limits. Furthermore, being able to use temperature ranges to provide adjustments to the power limits improves on Tidwell by being able to provide better control for power and temperature of the system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because to provide dynamically control for power and temperature of the system for improved power management of the system. Regarding claim 4, Tidwell teaches wherein determining to enter the power-limited mode for the memory device comprises throttling I/O throughput associated with the memory device. ([0103], “in some embodiments, “temperature throttling” is accomplished by reducing the total number of power credits to be allocated (in embodiments using a single type of power credit) or reducing the number of average power credits to be allocated (in embodiments using two or more types of power credits) when the temperature of the storage device is above a threshold temperature.” And [0116], “ the channel controller defers execution of a command if executing said command would require power credits in excess of the power credits available in the channel controller” where reducing the total number of power credits is interpreted as throttling throughput) Regarding claim 5, Tidwell teaches wherein identifying the temperature value associated with the memory device comprises receiving a temperature reading from a thermal sensor connected to the memory device. ([0048], “data storage system 100 includes storage device 120, which includes storage controller 128, power usage monitor 124 (e.g., a current sensor or power sensor, and/or one or more temperature sensors)” and [0069], “power usage monitor 124 is coupled to and provides board power measurement(s) and/or temperature measurements to storage controller 128.”) Regarding claim 6, Tidwell teaches wherein the operations further comprise: responsive to determining that the current power usage level of the memory device satisfies the power limit, identifying an I/O command referencing the memory device; estimating a power level associated with executing the I/O command; and responsive to determining that the power level satisfies the power limit, executing the I/O command. ([0116], “The channel controller defers execution of a command if executing said command would require power credits in excess of the power credits available in the channel controller (426) (e.g., power credits available can be the total number of power credits allocated to the respective channel controller during said epoch, minus the number of power credits assigned to command(s) currently being executed in the respective channel controller). As described in FIG. 3A, each command type has an assigned number of power credits (428), and execution of a respective command is deferred if the number of power credits assigned to the command type of the respective command exceeds the power credits available.” And [0019], “so long as there are sufficient power credits available, the channel controller selects a next command (from among the pending commands in the one or more command queues) for execution”) As to claims 8 and 14, Tidwell and Thomas teach these claims according to the reasoning provided in claim 1. As to claims 11 and 17, Tidwell and Thomas teach these claims according to the reasoning provided in claim 4. As to claims 12 and 18, Tidwell and Thomas teach these claims according to the reasoning provided in claim 5. As to claims 13 and 19, Tidwell and Thomas teach these claims according to the reasoning provided in claim 6. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-3, 9-10, and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tidwell and Thomas in view of Lasser (US 20150325290) Regarding claim 2, Tidwell teaches wherein determining the current power usage level of the memory device comprises: identifying a first number of partitions of the memory device executing read commands, a second number of partitions of the memory device executing write commands, a third number of partitions of the memory device executing force write commands, and a fourth number of partitions of the memory device executing refresh commands; and [0096], “In some embodiments, power credits usage per command type data structure 220 stores information based on different command types (e.g., read commands, write commands, erase commands)”) determining the current power usage level by adding a base power usage of the memory device to the first number of partitions weighted by a read command power usage value, the second number of partitions weighted by a write command power usage value, the third number of partitions weighted by a force write command power usage value, and the fourth number of partitions weighted by a refresh command power usage value. ([0109], “giving different weights to pending commands based on command type”) Tidwell teach partitions based on types of commands such as reads and writes but does not specifically mention other command like refresh and forced writes. Additionally, Tidwell teaches giving different weights based on command type but does not mention that the commands could be refresh or forced write. Lasser teaches a third number of partitions of the memory device executing force write commands, and a fourth number of partitions of the memory device executing refresh commands; the third number of partitions weighted by a force write command power usage value, and the fourth number of partitions weighted by a refresh command power usage value. ([0041], “The in-place refresh command 180 may exclude the data to be refreshed (since the data to be refreshed is stored at the particular location of the non-volatile memory 103, in this example). The in-place refresh command 180 is distinct from an “out-of-place” refresh command that refreshes data at a particular location by re-writing the data to another location.” And [0068], “the refresh all command may result in a sequence of actions including a forced write sequence (e.g., the forced write sequence 280 of FIG. 2)” Tidwell, Thomas, and Lasser are analogous art. Lasser is cited to teach a similar concept of operation of storage devices. Lasser teaches that some commands used in for storage device may include in-place refresh and out-of-place refresh (forced write) commands. Tidwell teaches any type of command to the storage device may have a number of partitions for executing and may be weighted by a power usage value for that command. Tidwell does not specifically mention a refresh or forced write command. Based on Lasser, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Tidwell and Thomas to include to a refresh or forced write command in its partitions and weighting. Furthermore, being able to partition and weight refresh or forced write commands improves on Tidwell and Thomas by being able to provide better control for power and temperature of the system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because to provide better control for power and temperature of the system. Regarding claim 3, Tidwell teaches wherein the base power usage of the memory device, the read command power usage value, the write command power usage value, the force write command power usage value, and the refresh command power usage value are predefined values based on the memory device. ([0096], “the table includes a single power credit usage value 314 (shown in FIG. 3A as the “average” power credit usage) for each command type, while in other embodiments the table includes two distinct power credit usage values (e.g., average power credit usage 314, and peak power credit usage 316) for each command type.”) As to claims 9-10 and 15-16, Tidwell, Thomas, and Lasser teach these claims according to the reasoning provided in claim 2-3, respectively. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 8, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHERI L HARRINGTON/Examiner, Art Unit 2176 January 15, 2026 /JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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Prosecution Timeline

Mar 11, 2024
Application Filed
Sep 08, 2025
Non-Final Rejection — §103
Dec 12, 2025
Examiner Interview Summary
Dec 12, 2025
Applicant Interview (Telephonic)
Dec 15, 2025
Response Filed
Jan 20, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
96%
With Interview (+27.2%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 307 resolved cases by this examiner. Grant probability derived from career allow rate.

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