DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed January 16, 2026 have been fully considered but they are not persuasive.
Specifically, Applicant argues that “[t]he claims of the pending application are unique and separate from the claims of U.S. Pat. No. 11,960,985. As a result the double patent rejection is misplaced, and applicant respectfully requests the examiner to withdraw the double patenting rejection.” And to support this argument, Applicant merely provides a copy of each of claims 1, 13, and 19 of the instant application, and a copy of each of claims 11, 1, and 17 of U.S. Patent No. 11,960,985, without any explanation showing how the corresponding claims “are unique and separate”.
Consequently, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the U.S. Patent No. 11,960,985. Additionally, the Examiner notes that previous grounds of rejection (and also included below) included a mapping of the claims that show how the claims of the instant application are an obvious variant and encompassed by the claims of U.S. Patent No. 11,960,985.
Double Patenting – Non-Statutory
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longa, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Orne, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Torrington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-2, 13-14, and 19 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 3, 11, and 17 of U.S. Patent No. 11,960,985. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Application 18/601,627
Patent 11,960,985
Claim 1
Claim 11
1. A device, comprising:
an integrated circuit, having:
11. A device, comprising:
a buffer;
an inference logic circuit;
voltage drivers; and
memory cells; and
memory cells;
a circuitry configured to:
generate, from input data, inputs to a set of artificial neurons;
… wherein the inference logic circuit is configured to:
generate, from the pixel values, inputs to a set of artificial neurons;
apply, according to the inputs, first voltages to a region of the memory cells having threshold voltages;
identify a region of the memory cells having threshold voltages …;
instruct the voltage drivers to apply first voltages to the region of the memory cells according to the inputs;
obtain, based on the region of the memory cells responsive to the first voltages, first data from an operation; and
obtain, based on the region of the memory cells responsive to the first voltages, first data from an operation of multiplication and accumulation …; and
apply functions to the first data to generate second data representative of outputs of the set of artificial neurons.
apply activation functions of the set of artificial neurons to the first data to generate second data representative of outputs of the set of artificial neurons.
Claim 2
Claim 11
2. The device of claim 1, wherein the circuitry includes voltage drivers configured in the integrated circuit to apply the first voltages.
11. … voltage drivers; and …
… instruct the voltage drivers to apply first voltages to the region of the memory cells according to the inputs; …
Claim 13
Claim 1
13. A method, comprising:
1. A method, comprising:
receiving, in a buffer in an integrated circuit device having an inference logic circuit, image data having pixel values;
generating, in an integrated circuit having memory cells and from input data, inputs to a set of artificial neurons;
generating, by the inference logic circuit and from the pixel values, inputs to a first set of artificial neurons;
applying, by the integrated circuit according to the inputs, first voltages to a region of the memory cells having threshold voltages;
identifying, by the inference logic circuit, a first region of memory cells of the integrated circuit device having threshold voltages …;
instructing, by the inference logic circuit, voltage drivers in the integrated circuit device to apply first voltages to the first region of memory cells according to the inputs;
obtaining, by the integrated circuit and based on the region of the memory cells responsive to the first voltages, first data from an operation applied on the inputs; and
obtaining, by the inference logic circuit and based on the first region of memory cells responsive to the first voltages, first data from an operation of multiplication and accumulation applied on … the inputs; and
applying, by the integrated circuit, functions to the first data to generate second data representative of outputs of the set of artificial neurons.
applying, by the inference logic circuits, activation functions of the first set of artificial neurons to the first data to generate second data representative of outputs of the first set of artificial neurons.
Claim 14
Claims 1 and 3
14. The method of claim 13, wherein the integrated circuit includes:
voltage drivers configured to apply the first voltages;
1. … instructing, by the inference logic circuit, voltage drivers in the integrated circuit device to apply first voltages to the first region of memory cells according to the inputs; …
current digitizers configured to obtain the first data; and
3. …digitizing currents in the plurality of lines as multiple of a predetermined amount of current to obtain the first data.
a logic circuit configured to implement the activation functions.
1. … applying, by the inference logic circuits, activation functions of the first set of artificial neurons to the first data to generate second data representative of outputs of the first set of artificial neurons.
Claim 19
Claim 17
19. An apparatus, comprising:
17. An apparatus, comprising:
a first integrated circuit die having memory cells; and
… a third integrated circuit die having a plurality of layers, each containing an array of memory cells having threshold voltages programmable to store data; …
a second integrated circuit die having a logic circuit;
… a second integrated circuit die having an image processing logic circuit, and an inference logic circuit; …
wherein the apparatus is configured to generate, from input data, inputs to a set of artificial neurons and apply, according to the inputs, first voltages to a region of the memory cells having threshold voltages;
… generate, from the pixel values, inputs to a set of artificial neurons;
identify a region of memory cells in the third integrated circuit die having threshold voltages …;
instruct the voltage drivers to apply read voltages to the region of memory cells according to the inputs; …
wherein the logic circuit is configured to apply functions to first data to generate second data representative of outputs of the set of artificial neurons; and
… apply activation functions of the set of artificial neurons to the first data to generate a second data representative of outputs of the set of artificial neurons.
wherein the first data is obtained, based on the region of the memory cells responsive to the first voltages, from an operation applied on the inputs.
… obtain, based on the region of memory cells responsive to the read voltages, first data from an operation of multiplication and accumulation applied on … the inputs;…
In view of the foregoing, Claims 1-2, 13-14, and 19 of the pending application are an obvious variant and encompassed by claims 1, 3, 11, and 17 of US Patent 11,960,985.
Allowable Subject Matter
Claims 3-12, 15-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISS S YODER III whose telephone number is (571)272-7323. The examiner can normally be reached M-F 9:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at (571) 272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.Y./Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638