DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11 and 14-20 are rejected under 35 U.S.C. 103 as unpatentable over Youssef et. al. (US 2014/0266461 A1) in view of Lee (US 2011/0260797 A1, cited by the applicant) and further in view of Reddy et. al. (US 2011/0291754 A1, also cited by the applicant).
Regarding claim 1, Youssef teaches an amplifier circuit portion arranged to amplify an input signal based on a gain control signal. Specifically, Youssef discloses a split Low Noise Amplifier (split LNA 400, Fig. 4, ¶ [0039]) that receives an input RF signal (RFin, Fig. 4) and amplifies it based on a gain control signal (Gain Mode, Fig. 4, ¶ [0039]).
Youssef also teaches the amplifier circuit portion comprising a plurality of amplifier cells having a common input and a common output. Specifically, Youssef discloses a first amplifier circuit (430, Fig. 4) and a second amplifier circuit (440, Fig. 4) coupled in parallel. These circuits share a common input (node X, Fig. 4) and a common output (RFout, Fig. 4, ¶ [0039]).
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Fig. 4A of Youssef reproduced for ease of reference.
Youssef further teaches that the amplifier cells can be biased to operate in a controllable gain mode (providing gain based on the control signal) or a fixed gain mode. Specifically, Youssef discloses that the amplifier circuits can be configured such that a gain transistor is applied a "variable bias current" to provide a range of gain values, or alternatively, applied a "fixed bias current" to provide a fixed gain when turned ON (¶ [0046]).
Youssef although describes the fixed gain operation and variable gain operation as alternative exemplary designs for the circuitry (e.g., "In one exemplary design... In another exemplary design..." ¶ [0046]), Youssef, however, does not explicitly teach a single amplifier cell that is actively configured to be selectively operable in both a fixed gain mode (providing a fixed, non-zero gain) and a controllable gain mode (providing variable gain) during the dynamic operation of the device.
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Fig. 1 of Lee reproduced for ease of reference.
Lee, in a similar field of endeavor, teaches an RF power amplifier system (100, Fig. 1) comprising a plurality of parallel amplifier unit cells (unit PAs 104, 105, which include sub-power-device cells PA1 to PAk, Fig. 1, ¶ [0031]-[0032]).
Lee explicitly teaches operating these individual amplifier cells in both a fixed discrete mode and a dynamically controllable variable mode within the exact same device. Specifically, Lee utilizes a switch controller (109, Fig. 1, ¶ [0032]) for discrete, fixed-gain switching (activating or deactivating specific sub-cells completely ON or OFF for coarse power control) AND a bias controller (108, Fig. 1, ¶ [0032], [0040]) for adaptive, variable biasing (dynamically varying the bias voltage VBIAS of the active cells based on required output power). Therefore, Lee teaches a single amplifier cell architecture capable of operating in both fixed and variable gain states.
It would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) to modify the parallel amplifier circuits (430 and 440, Fig. 4) of Youssef to be selectively operable in both a fixed gain mode and a controllable variable gain mode during active operation, exactly as taught by the dual-mode switching (109) and adaptive biasing architecture (108) of Lee.
The motivation to integrate the dual-mode (fixed and variable) cellular operation of Lee into the split amplifier architecture of Youssef is to achieve a highly optimized amplification system that provides a wide dynamic range while maximizing power efficiency and linearity. By implementing Lee’s teachings, a PHOSITA would leverage discrete fixed-gain steps for coarse power control (which saves DC power by entirely disabling unneeded amplifier cells) while simultaneously utilizing variable-gain adaptive biasing for fine-tuned, continuous power control across varying transmission environments (as explicitly sought after by Lee, ¶ [0005], [0032]).
Regarding claims 2, 4, 5, 6, 7, and 8 (Operating Modes and Configurations, these claims are bundled as they all relate to utilizing multiple cells in combinations of controllable, fixed, and disabled (OFF) modes to create different gain/sensitivity configurations) Youssef teaches multiple amplifier cells that are operable in controllable gain and fixed gain modes.
Youssef, however, does not explicitly teach a "disabled mode" (where the cell provides no amplification) utilized in "a plurality of different maximum/minimum gain configurations" using different combinations of these modes.
Lee explicitly teaches operating a plurality of parallel sub-power-device cells where individual cells can be actively switched ON or completely OFF (a disabled mode). Lee's switch controller specifically creates different maximum and minimum gain configurations by altering the combination of active and disabled cells.
It would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) to modify the split amplifier architecture of Youssef to include the disabled mode taught by Lee, allowing various combinations of cells to be fixed, variable, or completely disabled.
The motivation to include a disabled mode and discrete cell combinations is to save DC power by completely turning off unused parallel cells at lower required output power levels, thereby maximizing overall efficiency across a wide dynamic range (as explicitly taught by Lee).
Regarding claims 9, 10, and 11 (Cascode/Stacked Transistor Architecture, these claims relate to the internal cell structure comprising a gain transistor and a switch transistor in series and controlling gain via the switch transistor gate) Youssef teaches basic amplifier cells and manipulating bias currents to control gain.
Youssef, however, does not explicitly detail the amplifier cell comprising a gain transistor and a switch transistor connected in series (cascode) where operation is controlled by the switch transistor's gate.
Lee teaches sub-power-device cells comprising exactly this stacked arrangement. Specifically, Lee discloses a gain transistor, and a switch transistor stacked in series, where the first gate receives the RF input and the second gate (the switch transistor) receives a control signal to activate or deactivate the cell (fixing the voltage above a threshold for fixed gain).
It would have been obvious to a PHOSITA to implement the amplifier cells of Youssef using the stacked (cascode) switch and gain transistor architecture taught by Lee. Furthermore, for Claim 11, it would be an obvious design choice to apply the variable gain control signal to the gate of the switch transistor rather than (or in addition to) the gain transistor.
Using a series switch transistor allows for high RF isolation and simple discrete ON/OFF switching without loading or altering the impedance of the RF input matching network (which is connected to the gain transistor). Varying the switch gate voltage is a known, standard equivalent technique in RF IC design to modulate analog gain while preserving input matching.
Regarding claims 3 and 14 (Different Sizes / Binary Weighting, Claim 14 claims cells of different sizes. Claim 3 claims different combinations for minimum gain, which is inherent to sized segment control) Youssef teaches multiple amplifier cells.
Youssef, however, does not explicitly state that two or more of the amplifier cells have different sizes.
Reddy teaches a segmented power amplifier where different segments are activated based on varying segment combinations and bit-numbering schemes, which inherently relies on segments (amplifier cells) having different, weighted sizes (e.g., binary weighting) to achieve granular power steps.
It would have been obvious to a PHOSITA to modify the dual-mode parallel cells of Youssef and Lee to have different sizes, as taught by Reddy for sizing the parallel cells differently (e.g., binary scaling) provides finer resolution and a wider dynamic range of gain control using fewer overall segments, saving chip area while maintaining precise gain steps.
Regarding claims 15, 16, 17, 18, and 19 (Power Amplifier and Control Integration, these claims relate to deploying the circuit as a radio transmitter power amplifier with an integrated control circuit) Youssef teaches an integrated RF amplifier.
Youssef although describes an LNA (receiver), Youssef however, not explicitly teaches a Power Amplifier for a radio transmitter device with a dedicated control circuit portion.
Lee explicitly teaches an RF Power Amplifier system for transmissions. Lee further teaches a dedicated control circuit portion (mode controllers and switch controllers) arranged to generate gain control signals and configure the amplifier circuit.
It would have been obvious to a PHOSITA to deploy the hybrid fixed/variable parallel cell architecture of Youssef into a radio transmitter power amplifier device equipped with a control circuit, as taught by Lee.
The motivation is to achieve coarse and fine output power control in RF transmitters, combining the high efficiency of discrete cell switching with the high linearity of variable analog biasing.
Regarding claim 20 (Closed-Loop Power Feedback) Youssef teaches controlling amplifier gain based on a signal.
Youssef, however, does not teach sensing the transmission power and generating the gain control signal based on that sensed power.
Reddy explicitly teaches a power amplifier comprising a power detector connected to the amplifier output to sense transmission power, and a controller that dynamically adjusts the activation of the amplifier segments based on the detected power level.
It would have been obvious to a PHOSITA to incorporate the power detector and closed-loop feedback controller of Reddy into the transmitter device of Youssef and Lee.
The motivation to add closed-loop power sensing is to dynamically monitor and accurately maintain the desired RF output power level despite temperature fluctuations, voltage drops, or antenna load mismatch, which is critical for complying with strict wireless transmission regulations.
Allowable Subject Matter
Claims 12 and 13 are objected to as being dependent upon a rejected base claim 9 but would be allowable if rewritten in independent form including all the limitations of the base claim 9 and any intervening claims.
Claim 12 requires a highly specific circuit topology where an amplifier cell comprises an inverter that outputs to the gate of the switch transistor, and where the supply voltage of that inverter is modulated (selected to be a fixed voltage or a variable voltage based on the gain control signal) to control the gain. Claim 13 further specifies using a control enable signal to perform this supply voltage selection. None of the cited references (Youssef, Lee, or Reddy) teach or suggest driving a cascode switch transistor using an inverter whose own supply rail is dynamically modulated between fixed and variable voltage states to achieve dual-mode amplification. Because the prior art lacks this specific, unconventional gating architecture, claims 12 and 13 are allowable.
Conclusion
The prior arts, Buescher et al. (US 7,560,989 B2) , Kim et al. (US 11,984,856 B2), Dauphinee et al. (US 2009/0066414 A1), Burns et al.( US 2010/0073572 A1), Zolfaghari (US 2010/0330913 A1), van der Zanden et al.( US 2013/0120061 A1), Holenstein et al. (US 2014/0213209 A1) are made of record and not relied upon is considered pertinent to applicant's disclosure.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights