DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 25th, 2026 has been entered.
Claim Status
Claim 1 has been amended. Claims 10-11 remain cancelled. Claims 1-9 and 12-13 remain pending and are ready for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 11th, 2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7, 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication No. 2022/0036929 -- "Yu") in view of Madan et al. (US Publication No. 2023/0205706 -- "Madan") in further view of Kim et al. (US Publication No. 2020/0356305 -- "Kim").
Regarding claim 1, Yu teaches A memory controller controlling modes for processing requests for a memory device, the memory controller comprising: a bank group scheduler configured to generate a memory command corresponding to a memory request; (Yu paragraph [0006], According to an exemplary embodiment of the inventive concept, there is provided a memory device including a memory cell array including a first memory region and a second memory region; signal lines (e.g., command/address signal lines) configured to receive a command and an address from a source located outside the memory device; mode selector circuit configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command; a command converter circuit configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal; and an internal processor configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. A memory command can be generated in response to a memory request, via a scheduler component) an arbiter configured to select and output the memory command; and a Processing-in-Memory (PIM) management circuit configured to generate a PIM command corresponding to a PIM request and including a scheduler, (Yu paragraphs [0007-0008], According to an exemplary embodiment of the inventive concept, there is provided a method of operating a memory device including a memory cell array including a first memory region and a second memory region, and an internal processor configured to perform an internal processing operation, the method including receiving a command and an address from a source located outside the memory device through a pre-defined protocol interface; generating a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command; converting the received command into an internal processing operation command in response to activation of the internal processing mode selection signal; and the internal processor performing an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. According to exemplary embodiment of the inventive concept, there is provided a memory system including a memory device; and a memory controller configured to control the memory device by using a pre-defined protocol interface connected to the memory device. The memory device includes a memory cell array including a first memory region and a second memory region; an mode selector circuit configured to receive a command and an address from the memory controller through the pre-defined protocol interface and, based on the address received together with the command, generate a processing mode selection signal for controlling the memory device to enter an internal processing mode; a command converter circuit configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal; and an internal processor configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. An internal memory processing circuit may generate and transmit the command corresponding to said memory request, which can include executing a generated PIM command via a PIM engine, see Yu paragraph [0057], For example, when the PIM engine 250 performs an internal processing operation in response to the internal processing operation command PIM_CMD, the data DQ received through the data lines 134 and the data input/output circuit 260 may be stored in the PIM region 122 of the memory cell array 121 as internal processing data. The PIM engine 250 may store internal processing data according to an internal processing operation performed in response to the internal processing operation command PIM_CMD in the PIM region 122. Also see Yu paragraph [0111] for a PIM mode selector generating a command in response to a selection mode determination (i.e., PIM or normal mode)) a host interface circuit configured to receive the memory request and the PIM request from a host and a memory interface circuit configured to provide the memory command and the PIM command to the memory device (Yu paragraphs [0024-0025], The memory controller 112 includes a control register 116. The control register 116 may be used for initializing the memory device 120 and/or controlling the memory device 120 according to operating characteristics of the memory device 120. After the system 100 is powered up, the memory controller 112 may set the control register 116. The control register 116 may store various codes configured to allow the memory controller 112 to normally interoperate with the memory device 120. For example, codes indicating a frequency, a timing, and detailed operation parameters of the memory device 120 may be stored in the control register 116. Also, the control register 116 may store specific address information used by the controller 112 to physically or logically divide a memory cell array 121 of the memory device 120 according to an operation mode. For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124. The PIM region 122 may be a memory cell region accessed when the memory device 120 operates in an internal processing mode, and the normal memory region may be a memory cell region accessed when the memory device 120 operates in a normal mode. For example, a specific address may indicate an address used to access the PIM region 122 and may serve as a basic signal for allowing the memory device 120 to enter the internal processing mode. A specific address may include, for example, a stack identification signal, a channel address, or a bank address. According to embodiments, the specific address may include a combination of a stack identification signal, a channel address, and/or a bank address. The two modes (normal and in-memory processing) may be used depending upon various factors such as command frequency, timing, and other parameters. These commands may be transmitted from a host and controller, see Yu paragraphs [0022-0023], The host device 110 is a functional block for performing general computer operations in the system 100 and may correspond to a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or an application processor (AP). The host device 110 may include a memory controller 112 (e.g., a control circuit) that manages data transmission and reception to and from the memory device 120. The memory controller 112 may access the memory device 120 according to a memory request of the host device 110. The memory controller 112 includes a memory physical layer interface 114 for interfacing with the memory device 120. For example, the memory controller 112 may be used for selecting rows and columns corresponding to memory locations, writing data to memory locations, or reading written data. The memory physical layer interface 114 may be referred to as a memory PHY 114) wherein the modes include a normal mode for processing the memory request and a PIM mode for processing the PIM request, and wherein the PIM management circuit controls, according to a number of PIM commands, switching between the normal mode and the PIM mode (Yu paragraphs [0024-0025], The memory controller 112 includes a control register 116. The control register 116 may be used for initializing the memory device 120 and/or controlling the memory device 120 according to operating characteristics of the memory device 120. After the system 100 is powered up, the memory controller 112 may set the control register 116. The control register 116 may store various codes configured to allow the memory controller 112 to normally interoperate with the memory device 120. For example, codes indicating a frequency, a timing, and detailed operation parameters of the memory device 120 may be stored in the control register 116. Also, the control register 116 may store specific address information used by the controller 112 to physically or logically divide a memory cell array 121 of the memory device 120 according to an operation mode. For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124. The PIM region 122 may be a memory cell region accessed when the memory device 120 operates in an internal processing mode, and the normal memory region may be a memory cell region accessed when the memory device 120 operates in a normal mode. For example, a specific address may indicate an address used to access the PIM region 122 and may serve as a basic signal for allowing the memory device 120 to enter the internal processing mode. A specific address may include, for example, a stack identification signal, a channel address, or a bank address. According to embodiments, the specific address may include a combination of a stack identification signal, a channel address, and/or a bank address. The two modes (normal and in-memory processing) may be used depending upon various factors such as command frequency, timing, and other parameters) wherein the host interface circuit determines a host request provided from the host as the memory request when an address of the host request is included in a first memory space and determines the host request as the PIM request when the address of the host request is included in a second memory space (Yu Figure 1, see Ref. #124 and #122; paragraph [0025], For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124. The PIM region 122 may be a memory cell region accessed when the memory device 120 operates in an internal processing mode, and the normal memory region may be a memory cell region accessed when the memory device 120 operates in a normal mode. For example, a specific address may indicate an address used to access the PIM region 122 and may serve as a basic signal for allowing the memory device 120 to enter the internal processing mode. A specific address may include, for example, a stack identification signal, a channel address, or a bank address. According to embodiments, the specific address may include a combination of a stack identification signal, a channel address, and/or a bank address. The memory may be divided into a PIM region and a normal memory request region, and may include performing commands corresponding to said storage regions based on a specific address).
Yu does not teach including a scheduler, the PIM management circuit controls, according to a number of PIM commands, switching between the normal mode and the PIM mode, wherein the scheduler performs, by outputting a mode switching signal, a first switching corresponding to a switching from the PIM mode to the normal mode in response to an activation of a refresh signal.
However, Madan teaches including a scheduler, (A command queue and scheduler can be used to switch between normal and PIM mode operations, also see Madan paragraph [0043], Although implementations are depicted in the figures and described herein in the context of the command queue 170 being implemented as a single element, implementations are not limited to this example and according to an implementation, the command queue 170 is implemented by multiple elements, for example, a separate command queue for each of the banks in the memory module 140. The scheduler 172 schedules memory commands for processing. According to an implementation, the scheduler 172 selects commands for processing based upon various selection criteria, as described in more detail hereinafter) the PIM management circuit controls, according to a number of PIM commands, switching between the normal mode and the PIM mode (Madan paragraph [0030], An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. Examples of selection criteria include, without limitation, command allocation bandwidth, a number of pending commands, an amount of time or number of cycles since a most recent command was issued, a presence of a marker, or global age, etc. The execution of a given command, requiring the switching of a PIM or normal command mode, can be issued based on the number of pending commands); wherein the scheduler performs, by outputting a mode switching signal (A command queue and scheduler can be used to switch between normal and PIM mode operations, also see Madan paragraph [0043], Although implementations are depicted in the figures and described herein in the context of the command queue 170 being implemented as a single element, implementations are not limited to this example and according to an implementation, the command queue 170 is implemented by multiple elements, for example, a separate command queue for each of the banks in the memory module 140. The scheduler 172 schedules memory commands for processing. According to an implementation, the scheduler 172 selects commands for processing based upon various selection criteria, as described in more detail hereinafter)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu with those of Madan. Madan teaches switching between a normal command operation and a PIM command operation based on a variety of factors, including the number of pending commands. As switching between PIM mode and normal mode is a demanding process, optimizing the switching based on the number of commands can improve the functioning of the system by requiring less overall switching (Madan paragraph [0032], The approach of using a single All Banks entry in the page table to track the status of memory elements after processing the most recent PIM command allows the memory controller to efficiently manage, both from a computational cost and power consumption perspective, PIM commands and non-PIM commands without having to isolate PIM commands and non-PIM commands, which can cause a large performance penalty).
Yu in view of Madan does not teach a first switching corresponding to a switching from the PIM mode to the normal mode in response to an activation of a refresh signal.
However, Kim teaches a first switching corresponding to a switching from the PIM mode to the normal mode in response to an activation of a refresh signal (Kim paragraphs [0105-0106], The state diagram 600 of FIG. 6 is in many respects the same as a corresponding state diagram for a conventional Dynamic Random Access Memory (DRAM). In an embodiment, the state machine corresponding to the state machine 600 changes states in response to a PIM read command (PIM RD) and a PIM write command (PIM WR), which are PIM commands, as well as changing states in response to a read command (RD), a write command (RD), an Activate command (AC), a Precharge command (PRE), and a Refresh command (REF) which are conventional DRAM commands. Kim teaches utilizing normal commands states and PIM command states, and can switch from PIM commands to normal command state in response to conventional commands, such as a precharge or refresh command, which can involve signal activation, such as in Kim paragraph [0064], FIG. 4A shows data structure of a memory command according to an embodiment, and FIG. 4B shows data structure of a PIM command according to an embodiment. The memory command and PIM command may be communicated from a memory controller to a memory device via a common interface. In an embodiment, the interface may be signals according to a memory standard).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu and Madan with those of Kim. Kim teaches switching between PIM and normal command operation in various scenarios, including activation of a refresh signal, which can allow the memory device to perform the command (i.e., refresh) without interruption/delay (i.e., see Kim paragraph [0114], First, it is possible to prevent the processing of a memory command from being unconditionally interrupted by the processing of a PIM command. Accordingly, since a memory command can be scheduled and processed while a collision does not occur during processing of a PIM command, performance degradation of a memory system can be prevented)
Regarding claim 2, Yu in view of Madan in further view of Kim teaches The memory controller of claim 1, wherein the PIM management circuit includes: a command queue configured to store the PIM command; a scheduler configured to control switching between the normal mode and the PIM mode; (Madan paragraph [0041], FIG. 1C depicts an example implementation of the memory controller 130 and includes a command queue 170, a scheduler 172, processing logic 174, command metadata 176 and a page table 178. The memory controller 130 includes fewer or additional elements that vary depending upon a particular implementation and that are not depicted in the figures and described herein for purposes of explanation. In addition, the functionality provided by the various elements of the memory controller 130 are combined in any manner, depending upon a particular implementation. A command queue and scheduler can be used to switch between normal and PIM mode operations, also see Madan paragraph [0043], Although implementations are depicted in the figures and described herein in the context of the command queue 170 being implemented as a single element, implementations are not limited to this example and according to an implementation, the command queue 170 is implemented by multiple elements, for example, a separate command queue for each of the banks in the memory module 140. The scheduler 172 schedules memory commands for processing. According to an implementation, the scheduler 172 selects commands for processing based upon various selection criteria, as described in more detail hereinafter) a command generator configured to generate a preparation command during a switching step to the normal mode or to the PIM mode; a command selection circuit configured to select an output of the command queue or an output of the command generator; (Yu paragraphs [0047-0048], The PIM mode selector 210 may activate the PIM mode selection signal PIM_SEL when a specific address is included in the address ADDR received through the command/address signal lines 132. By activating the PIM mode selection signal PIM_SEL, the memory device 120 may operate in the internal processing mode. The PIM mode selector 210 may deactivate the PIM mode selection signal PIM_SEL when no specific address is included in the address ADDR received through the command/address signal lines 132. For example, the PIM mode selection signal PIM_SEL may be activated by setting it the first logic level and deactivated by setting it to the second logic level. By deactivating the PIM mode selection signal PIM_SEL, the memory device 120 may operate in the normal mode. The PIM mode selection signal PIM_SEL may be provided to the first switch 231 and the second switch 232. The first switch 231 may selectively connect the command/address signal lines 132 to input signal lines 221 or internal command signal lines 240 of the PIM command converter 126 in response to the PIM mode selection signal PIM_SEL. The second switch 232 may selectively connect output signal lines 222 or the internal command signal lines 240 of the PIM command converter 126 to the memory cell array 121 and the PIM engine 250 in response to the PIM mode selection signal PIM_SEL. A normal command can be generated during the determination of the command operation mode. This can then be output as a normal command instead of the PIM command queue operation) and a control circuit configured to control the command generator and the command selection circuit according to control of the scheduler (A command queue and scheduler can be used to control operations and command selection, see Madan paragraph [0043], Although implementations are depicted in the figures and described herein in the context of the command queue 170 being implemented as a single element, implementations are not limited to this example and according to an implementation, the command queue 170 is implemented by multiple elements, for example, a separate command queue for each of the banks in the memory module 140. The scheduler 172 schedules memory commands for processing. According to an implementation, the scheduler 172 selects commands for processing based upon various selection criteria, as described in more detail hereinafter).
Regarding claim 7, Yu in view of Madan in further view of Kim teaches The memory controller of claim 2, wherein the scheduler determines to perform a second switching corresponding to a switching from the PIM mode to the normal mode when all PIM commands stored in the command queue are processed, a refresh signal is activated, a calibration signal is activated, or a combination thereof (Kim paragraphs [0107-0109], States of the state diagram 600 include an idle state S10, a bank active state S20, a write state S30, a read state S40, a precharge state S50, and a refresh state S60. When the Activate command ACT is input in the idle state S10, the state transitions to the bank active state S20, and in an embodiment a row of a bank determined according to an address associated with the Activate command is placed in the activated state, so that data can be read from and written to that row. When the refresh command REF is input in the idle state S10, the state transitions to the refresh state S60. When the write command WR or PIM write command PIM WR is input in the bank active state S20, the state transitions to the write state S30. When the read command RD or the PIM read command PIM RD is input in the bank active state S20, the state transitions to the read state S40. When the precharge command PRE is input in the bank active state S20, the state transitions to the precharge state S50. A refresh command can be implemented to switch from the PIM command state to a normal state (i.e., mode) of operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu, Madan with those of Kim. Kim teaches using a refresh command to change the PIM commands from an active state to an idle state, resulting in normal command operation. This allows the system to transition from the PIM command operation to normal command operation easily and efficiently (Kim paragraphs [0112-0114], When the precharge operation terminates in the precharge state S50, the state transitions to the idle state S10. When the refresh operation terminates in the refresh state S60, the state transitions to the idle state S10. Whenever the state machine transitions to the precharge state S50, the active row in the bank is deactivated. As shown in FIG. 6, memory commands and PIM commands are processed by the state machine corresponding to the state diagram 600 in the same way, which has the following advantages. First, it is possible to prevent the processing of a memory command from being unconditionally interrupted by the processing of a PIM command. Accordingly, since a memory command can be scheduled and processed while a collision does not occur during processing of a PIM command, performance degradation of a memory system can be prevented).
Regarding claim 9, Yu in view of Madan in further in view of Kim teaches The memory controller of claim 7, wherein when the refresh signal is activated, the scheduler determines to perform the second switching after delaying a predetermined time (Kim paragraphs [0046-0048], The command scheduler 150 selects and outputs memory commands and PIM commands stored in the command queue 140 to the memory device 200 in consideration of timing constraints necessary for operation of the memory device 200. The timing constraint is predefined through standards or the like, and a detailed description thereof will be omitted. In an embodiment, the command scheduler 150 may consider additional constraints in addition to the timing constraints. The timing for the switching between operation states (PIM and normal) can be delayed based on given timing constraints and factors considered by the scheduler component, also see Kim paragraph [0074], The memory device 200 may further refer to an address provided to the memory device 200 in association with a PIM command in the same manner as the memory device 200 refers to an address provided to the memory device 200 in association with a memory command. The address may be provided to the memory device over different signals than those used to communicate the memory or PIM command, over the same signals as those used to communicate the memory or PIM command by using time multiplexing, or a combination thereof) after the refresh signal is activated (Kim paragraphs [0107-0109], States of the state diagram 600 include an idle state S10, a bank active state S20, a write state S30, a read state S40, a precharge state S50, and a refresh state S60. When the Activate command ACT is input in the idle state S10, the state transitions to the bank active state S20, and in an embodiment a row of a bank determined according to an address associated with the Activate command is placed in the activated state, so that data can be read from and written to that row. When the refresh command REF is input in the idle state S10, the state transitions to the refresh state S60. When the write command WR or PIM write command PIM WR is input in the bank active state S20, the state transitions to the write state S30. When the read command RD or the PIM read command PIM RD is input in the bank active state S20, the state transitions to the read state S40. When the precharge command PRE is input in the bank active state S20, the state transitions to the precharge state S50. A refresh command can be implemented to switch from the PIM command state to a normal state (i.e., mode) of operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu, Madan with those of Kim. Kim teaches using a refresh command to change the PIM commands from an active state to an idle state, resulting in normal command operation. This allows the system to transition from the PIM command operation to normal command operation easily and efficiently (Kim paragraphs [0112-0114], When the precharge operation terminates in the precharge state S50, the state transitions to the idle state S10. When the refresh operation terminates in the refresh state S60, the state transitions to the idle state S10. Whenever the state machine transitions to the precharge state S50, the active row in the bank is deactivated. As shown in FIG. 6, memory commands and PIM commands are processed by the state machine corresponding to the state diagram 600 in the same way, which has the following advantages. First, it is possible to prevent the processing of a memory command from being unconditionally interrupted by the processing of a PIM command. Accordingly, since a memory command can be scheduled and processed while a collision does not occur during processing of a PIM command, performance degradation of a memory system can be prevented).
Regarding claim 12, Yu in view of Madan in further view of Kim teaches The memory controller of claim 1, wherein the first memory space corresponds to a storage space in the memory device accessed by the memory request and the second memory space corresponds to a storage space in the memory device accessed by the PIM request (Yu Figure 1, see Ref. #124 and #122; paragraph [0025], For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124. The PIM region 122 may be a memory cell region accessed when the memory device 120 operates in an internal processing mode, and the normal memory region may be a memory cell region accessed when the memory device 120 operates in a normal mode. For example, a specific address may indicate an address used to access the PIM region 122 and may serve as a basic signal for allowing the memory device 120 to enter the internal processing mode. A specific address may include, for example, a stack identification signal, a channel address, or a bank address. According to embodiments, the specific address may include a combination of a stack identification signal, a channel address, and/or a bank address. The memory may be divided into a PIM region and a normal memory request region, and may include performing commands corresponding to said storage regions based on a specific address).
Claim(s) 3-4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Madan in further view of Kim as applied to claim 2 above, and further in view of Alsop et al. (US Publication No. 2024/0004653 -- "Alsop").
Regarding claim 3, Yu in view of Madan in further view of Kim and further in view of Alsop teaches The memory controller of claim 2, wherein the scheduler determines to perform a first switching corresponding to switching from the normal mode to the PIM mode when a number of PIM commands stored in the command queue exceeds a threshold (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. When the command PIM queue reaches a predetermined level, the PIM commands may be executed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu and Madan and Kim with those of Alsop. Alsop teaches using a PIM command queue with a threshold that will execute PIM commands when exceeded. This can prevent the PIM command queue from becoming overloaded or deadlocked (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. To avoid deadlock, the active processor thread TO is checkpointed by storing the values in near-processing local storage to memory, or some other storage. For example, the concurrency controller 224 issues commands to store the values in near-memory processing registers to memory and the memory controller 220 ensures that those memory locations are not overwritten).
Regarding claim 4, Yu in view of Madan in further view of Kim and further in view of Alsop teaches The memory controller of claim 3, wherein when the scheduler determines to perform the first switching, the control circuit controls the bank group scheduler so that a new memory request is not input to the bank group scheduler and so that a bank flush operation is performed to process all memory commands stored in the bank group scheduler (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. To avoid deadlock, the active processor thread TO is checkpointed by storing the values in near-processing local storage to memory, or some other storage. For example, the concurrency controller 224 issues commands to store the values in near-memory processing registers to memory and the memory controller 220 ensures that those memory locations are not overwritten. Another processor thread is selected to be the active processor thread and the PIM commands for that processor thread are processed as described herein. After that processor thread has completed, the checkpointed processor thread is selected as the active processor thread and register values for that processor thread that were saved to memory are reloaded into the registers of the near-memory processing element and processing of the PIM command sequence for that processor thread then resumes. This may be repeated for any number of processor threads as necessary to prevent the command queue 222 from becoming deadlocked. The normal (i.e., non-PIM) commands may be completely executed and cleared from the queue before the PIM commands resume).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu and Madan and Kim with those of Alsop. Alsop teaches using a PIM command queue with a threshold that will execute PIM commands when exceeded. This can prevent the PIM command queue from becoming overloaded or deadlocked (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. To avoid deadlock, the active processor thread TO is checkpointed by storing the values in near-processing local storage to memory, or some other storage. For example, the concurrency controller 224 issues commands to store the values in near-memory processing registers to memory and the memory controller 220 ensures that those memory locations are not overwritten).
Regarding claim 13, Yu in view of Madan in further view of Kim and further in view of Alsop teaches The memory controller of claim 12, wherein an address included in the PIM request is used to identify a unit space of a PIM input buffer included in the memory device when the PIM request is a PIM write request, (Alsop paragraph [0037], In the example depicted in FIG. 2C, the command queue 222 stores data that indicates a corresponding processor thread (“Thread ID”) and whether a PIM command is the final PIM command in a PIM command sequence (“Is_Final”). As described in more detail hereinafter, this information may be explicitly indicated in a PIM command, for example by one or more bits, or determined from other information in a PIM command, such as address information. This information is used to issue PIM commands on a processor thread-by-processor thread basis to avoid interference, as described in more detail hereinafter. PIM commands can be stored in a PIM input buffer based on address information (i.e., PIM command queue), which can be a buffer, as seen in Alsop paragraph [0039], The command queue 222 is implemented by any type of storage capable of storing memory commands, such as registers, a local cache, a buffer, etc) and wherein an address included in the PIM request is used to identify a unit space of a PIM output buffer included in the memory device when the PIM request is a PIM read request or a PIM execution request (Kim paragraph [0007], In accordance with the present teachings, a memory device according to an embodiment may include a command decoder configured to decode a memory command representing a read or a write operation in the memory device and decode a PIM command representing a processing operation in the memory device; a bank to store data; an input/output (IO) buffer configured to input or output data; a shared bus configured to transfer data between the bank and the IO buffer; and a processing circuit configured to be connected with the shared bus and the bank and to perform a processing operation according to a control by the command decoder, wherein the bank is controlled by the command decoder to perform a memory command while the processing circuit performs a processing operation by a PIM command. A command queue may be used as an I/O buffer to store PIM commands corresponding to PIM execution commands, which can also be based on the corresponding addresses for PIM commands, see Kim paragraph [0023], the PIM requests may be communicated to the memory controller 100 via a common interface. The memory controller may also receive other information associated with the memory requests and PIM requests (such as addresses) via the common interface).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu and Madan and Kim with those of Alsop. Alsop teaches using a PIM command queue with a threshold that will execute PIM commands when exceeded. This can prevent the PIM command queue from becoming overloaded or deadlocked (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. To avoid deadlock, the active processor thread TO is checkpointed by storing the values in near-processing local storage to memory, or some other storage. For example, the concurrency controller 224 issues commands to store the values in near-memory processing registers to memory and the memory controller 220 ensures that those memory locations are not overwritten).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Madan in further view of Kim in further view of Alsop as applied to claim 4 above, and further in view of Kasibhatla et al. (US Patent No. 11,074,961 -- "Kasibhatla").
Regarding claim 5, Yu in view of Madan in further view of Kim and further in view of Alsop and further in view of Kasibhatla teaches The memory controller of claim 4, wherein when the bank flush operation has processed all the memory commands stored in the bank group scheduler, (Alsop paragraph [0070], In many situations, PIM command sequences are relatively short and the final PIM command in a PIM command sequence is issued before the command queue 222 becomes full. In other situations, however, it is possible that the final PIM command in a PIM command sequence is not issued before the command queue 222 becomes full. This may occur for a variety of reasons, for example, a PIM command sequence is unusually long or the final PIM command in a PIM command sequence is delays. According to an implementation, deadlock of the command queue 222 is avoided by checkpointing the PIM command sequence for the active processor thread when the number of available slots in the command queue 222 falls below a specified threshold and another processor thread is selected for processing. For example, suppose that the active processor thread is TO and the number of available slots in the command queue 222 falls below a specified threshold, indicating that the command queue 222 may become deadlocked before the PIM command sequence for the active processor thread TO is completed. To avoid deadlock, the active processor thread TO is checkpointed by storing the values in near-processing local storage to memory, or some other storage. For example, the concurrency controller 224 issues commands to store the values in near-memory processing registers to memory and the memory controller 220 ensures that those memory locations are not overwritten. Another processor thread is selected to be the active processor thread and the PIM commands for that processor thread are processed as described herein. After that processor thread has completed, the checkpointed processor thread is selected as the active processor thread and register values for that processor thread that were saved to memory are reloaded into the registers of the near-memory processing element and processing of the PIM command sequence for that processor thread then resumes. This may be repeated for any number of processor threads as necessary to prevent the command queue 222 from becoming deadlocked. The normal (i.e., non-PIM) commands may be completely executed and cleared from the queue before the PIM commands resume) the controller controls the command generator and the command selection circuit so that an all-bank precharge command and a Mode Register Set (MRS) command for a mode switching are provided to the memory device (Kasibhatla column 11; lines 25-44, The command/address buffer 310 may receive control signals corresponding to the command CMD from the memory controller 114 through the first channel CH1. The control signals may include, for example, a write enable signal /WE, a row address strobe signal /RAS, a column address strobe signal /CAS, and/or a chip selection signal /CS, and the command CMD may include, for example, an active command, a read command, a write command, and/or a precharge command. The command/address buffer 310 may receive an address ADDR from the memory controller 114 through the first channel CH1. The address ADDR may include a row address for addressing a row of the memory cell array 122 and a column address for addressing a column of the memory cell array 122. The command/address buffer 310 may transmit the row address and the column address to the row/column decoder 312. The controller can transmit a precharge command and a mode switch command for PIM and normal mode command operation for the memory device, for mode switching see Kasibhatla column 5; lines 3-19, According to an embodiment, the PIM agent 116 may activate and transmit the internal processing mode signal IPM to the memory device 120. The internal processing mode signal IPM may be transmitted to the memory device 120 as a combination of several signals, such as a command combination, a mode register set (MRS), or an address combination. In this case, the internal processing mode signal IPM may be transmitted to the memory device 120 through the buses and/or signal lines of the first channel CH1 between the host device 110 and the memory device 120. The internal processing mode signal IPM may allow the memory device 120 to operate in the internal processing mode. In the internal processing mode, an internal processing operation may include accessing the memory cell array 122 to perform a processing operation on the data stored in the memory cell array 122).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu, Madan, Kim and Alsop with those of Kasibhatla. Kasibhatla teaches using a PIM command queue as well as a scheduler which can implement a precharge command as well as switch between normal and PIM mode commands via a controller component. This can provide additional flexibility for the memory system allowing for faster operation mode switching improving performance (Kasibhatla column 1; lines 45-62, In order to improve the system performance, a memory device including an internal processor is developed to perform some of the computation operations of the host by internal processing. The computational workload of the host may be reduced due to the internal processing of the memory device. However, in order to prevent a collision between the internal processing and the processing by the host, the memory device may need to perform an arbiter function to determine a priority thereof. Also, the memory device may perform an operation of reading and writing in the memory device by internal processing. In this case, when data stored in a cache of the host is changed in the memory device, the data in the cache is not the latest data, whereby there may be a limitation in the coherence of cache data. Accordingly, the memory device may need to perform a virtual memory management function such as a virtual memory address translation across the host and the memory device).
Regarding claim 6, Yu in view of Madan in further view of Kim and further in view of Alsop and further in view of Kasibhatla teaches The memory controller of claim 5, wherein when the MRS command is provided to the memory device, the controller controls the command selection circuit so that an output of the command queue is selected (Kasibhatla column 5; lines 3-19, According to an embodiment, the PIM agent 116 may activate and transmit the internal processing mode signal IPM to the memory device 120. The internal processing mode signal IPM may be transmitted to the memory device 120 as a combination of several signals, such as a command combination, a mode register set (MRS), or an address combination. In this case, the internal processing mode signal IPM may be transmitted to the memory device 120 through the buses and/or signal lines of the first channel CH1 between the host device 110 and the memory device 120. The internal processing mode signal IPM may allow the memory device 120 to operate in the internal processing mode. In the internal processing mode, an internal processing operation may include accessing the memory cell array 122 to perform a processing operation on the data stored in the memory cell array 122. The command may be selected from the command queue, such as in Kasibhatla column 13; lines 23-36, When the internal processing information IPI read from the memory cell array 122 includes or is an internal processing operation command IPCMD indicating a type of the internal processing operation, the internal processor 320 may store an internal processing read command PIM_READ and/or an internal processing write command PIM_WRITE constituting the internal processing operation command IPCMD in the command queue 324. The command queue 324 may store the internal processing operation command IPCMD including at least one of the internal processing read command PIM_READ and the internal processing write command PIM_WRITE).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu, Madan, Kim and Alsop with those of Kasibhatla. Kasibhatla teaches using a PIM command queue as well as a scheduler which can implement a precharge command as well as switch between normal and PIM mode commands via a controller component. This can provide additional flexibility for the memory system allowing for faster operation mode switching improving performance (Kasibhatla column 1; lines 45-62, In order to improve the system performance, a memory device including an internal processor is developed to perform some of the computation operations of the host by internal processing. The computational workload of the host may be reduced due to the internal processing of the memory device. However, in order to prevent a collision between the internal processing and the processing by the host, the memory device may need to perform an arbiter function to determine a priority thereof. Also, the memory device may perform an operation of reading and writing in the memory device by internal processing. In this case, when data stored in a cache of the host is changed in the memory device, the data in the cache is not the latest data, whereby there may be a limitation in the coherence of cache data. Accordingly, the memory device may need to perform a virtual memory management function such as a virtual memory address translation across the host and the memory device).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Madan in further view of Kim as applied to claim 7 above, and further in view of Kasibhatla.
Regarding claim 8, Yu in view of Madan in further view of Kim and further in view of Kasibhatla teaches The memory controller of claim 7, wherein when the scheduler determines to perform the second switching, the control circuit controls the command generator and the command selection circuit so that an all-bank precharge command and a Mode Register Set (MRS) command for a mode switching are provided to the memory device (Kasibhatla column 5; lines 3-19, According to an embodiment, the PIM agent 116 may activate and transmit the internal processing mode signal IPM to the memory device 120. The internal processing mode signal IPM may be transmitted to the memory device 120 as a combination of several signals, such as a command combination, a mode register set (MRS), or an address combination. In this case, the internal processing mode signal IPM may be transmitted to the memory device 120 through the buses and/or signal lines of the first channel CH1 between the host device 110 and the memory device 120. The internal processing mode signal IPM may allow the memory device 120 to operate in the internal processing mode. In the internal processing mode, an internal processing operation may include accessing the memory cell array 122 to perform a processing operation on the data stored in the memory cell array 122. The command may be selected from the command queue, such as in Kasibhatla column 13; lines 23-36, When the internal processing information IPI read from the memory cell array 122 includes or is an internal processing operation command IPCMD indicating a type of the internal processing operation, the internal processor 320 may store an internal processing read command PIM_READ and/or an internal processing write command PIM_WRITE constituting the internal processing operation command IPCMD in the command queue 324. The command queue 324 may store the internal processing operation command IPCMD including at least one of the internal processing read command PIM_READ and the internal processing write command PIM_WRITE. The signal can also include a precharge command, see Kasibhatla column 11; lines 25-44, The command/address buffer 310 may receive control signals corresponding to the command CMD from the memory controller 114 through the first channel CH1. The control signals may include, for example, a write enable signal /WE, a row address strobe signal /RAS, a column address strobe signal /CAS, and/or a chip selection signal /CS, and the command CMD may include, for example, an active command, a read command, a write command, and/or a precharge command. The command/address buffer 310 may receive an address ADDR from the memory controller 114 through the first channel CH1. The address ADDR may include a row address for addressing a row of the memory cell array 122 and a column address for addressing a column of the memory cell array 122. The command/address buffer 310 may transmit the row address and the column address to the row/column decoder 312).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu, Madan, and Kim with those of Kasibhatla. Kasibhatla teaches using a PIM command queue as well as a scheduler which can implement a precharge command as well as switch between normal and PIM mode commands via a controller component. This can provide additional flexibility for the memory system allowing for faster operation mode switching improving performance (Kasibhatla column 1; lines 45-62, In order to improve the system performance, a memory device including an internal processor is developed to perform some of the computation operations of the host by internal processing. The computational workload of the host may be reduced due to the internal processing of the memory device. However, in order to prevent a collision between the internal processing and the processing by the host, the memory device may need to perform an arbiter function to determine a priority thereof. Also, the memory device may perform an operation of reading and writing in the memory device by internal processing. In this case, when data stored in a cache of the host is changed in the memory device, the data in the cache is not the latest data, whereby there may be a limitation in the coherence of cache data. Accordingly, the memory device may need to perform a virtual memory management function such as a virtual memory address translation across the host and the memory device).
Response to Arguments
Applicant’s arguments, see pages 1-3 (numbered pages 5-7), filed February 3rd, 2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yu et al. (US Publication No. 2022/0036929 -- "Yu") in view of Madan et al. (US Publication No. 2023/0205706 -- "Madan") in further view of Kim et al. (US Publication No. 2020/0356305 -- "Kim").
The applicant's arguments regarding the amended independent claim 1 overcome the previous rejection and references, and now have the Kim reference attached above added. The Kim reference has been specifically added to teach the concept of changing an operation mode in response to a refresh command, as described in further detail in the rejection above. In light of the newly applied reference, the 35 USC 103 Rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US Patent No. 11,079,936) teaches using a PIM mode and a normal command mode, and can describe using a normal command mode for various generic memory functions, such as a refresh signal (i.e., see Chang column 3; lines 10 25, According to one or more example embodiments of the present invention, an interface of a memory device including a processor in memory, includes: a control bus configured to transfer commands from an external host to the memory device; and a data bus configured to transfer data between the memory device and the host; wherein the interface is configured to transfer the commands to set the memory device to operate in a PIM mode to compute data, and to set the memory device to operate in a normal mode to perform memory functions, and the memory device is configured to translate memory commands into logic commands to compute the data according to the logic commands when in the PIM mode, and to perform the memory functions according to the memory commands when in the normal mode. Also see column 15; lines 19-30).
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/J.C.K./ Examiner, Art Unit 2133/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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