DETAILED ACTION
Claims 1, 3-16, 18-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Final.
Claims 1, 7 and 11 are independent claims. Claims 2-6, 8-10, 12-16 and 18-20 are dependent claims. Claims 2 and 17 have been canceled.
This action is responsive to the following communication: the response filed on 12-23-2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2024/0372473 (hereinafter, “Zafarana”) in view of U.S. Publication No. 2023/0051490 (hereinafter, “Domingo”).
As per claim 7, Zafarana discloses a convertor circuit, comprising:
a plurality of power stage circuits, comprising a plurality of current feedback terminals and a plurality of temperature feedback terminals; and (Fig. 1 illustrates power modules comprising current terminals 112, 118, 124 and temperature terminals 114, 120, 126)
a control circuit, coupled to the plurality of current feedback terminals, coupled with the plurality of temperature feedback terminals at a node, and (Fig. 1 illustrates voltage regulator 102 coupled to the said terminals at a Vin/Vout node)
confiqured to receive a hiqhest temperature signal throuqh the node, to obtain a hiqhest temperature value of the plurality of power stage circuits according to the highest temperature signal, (¶ [0013] discloses a controller that may be further configured to indicate whether “the power module has a same or a higher temperature than a parallel power module”. Also, ¶ [0069] )
wherein the plurality of power staqe circuits are confiqured to output a plurality of current feedback signals to the control circuit throuqh the plurality of current feedback terminals; (inter alia: Based on the feedback signal received through the feedback terminal 128, the voltage regulator 102 controls the various phases to control the voltage output V.sub.OUT and/or the current provided; ¶ [0034] )
outputs a signal to the control circuit through at least corresponding one of the plurality of feedback terminals; (inter alia: Based on the feedback signal received through the feedback terminal 128, the voltage regulator 102 controls the various phases to control the voltage output V.sub.OUT and/or the current provided; ¶ [0034] )
Zafarana does not distinctly disclose the following:
wherein in response to at least one failure event of at least one of the plurality of power stage circuits, the at least one of the plurality of power stage circuits controls the highest temperature signal to be in a preset voltage level, and
outputs at least one failure code.
However, Domingo explicitly discloses the following:
wherein in response to at least one failure event of at least one of the plurality of power stage circuits, ( ¶ [008] states “the monitored status indicates that one of the multiple power converters experiences the event such as a failure.” ) the at least one of the plurality of power stage circuits controls the highest temperature signal to be in a preset voltage level, and (¶ [0127] discloses “status information signal 125” which indicates that the status information signal represents “a first parameter (such as such as the highest temperature of any of the power converters)”. Based on the status information containing an “error” detection in relation to an output voltage from the plurality of power converters, controller 14 is may control a plurality of parameters such that the output voltage is “within a desired voltage range”. [0074]-[0086] Simply put: the system is designed to use feedback signals to detect error failures from plurality of voltage converters causing the output voltages not being within the desired range. In response to that the system is further configured to control parameters that leads the output voltages to be within a desired range )
outputs at least one failure code. (Domingo discloses the concept where multiple power converters may experience an event “failure” signal. ¶ [008] This signal may “encoded in any suitable manner” ¶ [0009]
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Zafarana and Domingo because both references are in the same field of endeavor. Domingo’s teaching of sending feedback signals for detecting power converter failure would enhance Zafarana's system by eliminating additional command steps, thus expediting failure detection.
Allowable Subject Matter
Claims 1, 3-6, 9-16, 18-20 are allowed.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Remarks
Applicant's arguments filed on 12-23-2026 have been fully considered but they are not persuasive to the extent that is applicable to the claims.
I. Rejections under 35 U.S.C. §103
Independent Claim 7
Claim 7 is currently rejected under 35 U.S.C. § 103 over over U.S. Publication No. 2024/0372473 (hereinafter, “Zafarana”) in view of U.S. Publication No. 2023/0051490 (hereinafter, “Domingo”)
During examination of patent application, claims are given their broadest reasonable interpretation under the BRI standard. Furthermore, under the BRI, words of the claim must be given their plain meaning. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Limitations appearing in the specification but not recited in the claim are not read into the claim. In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-551 (CCPA 1969)” (MPEP p 2100-8, c 2, I 45-48; p 2100-9, c 1, l 1-4).
As per claim 7, Applicants assert that the cited prior art allegedly fails to disclose at least “a plurality of power staqe circuits, comprisinq a plurality of current feedback terminals and a plurality of temperature feedback terminals; and a control circuit, coupled to the plurality of current feedback terminals, coupled with the plurality of temperature feedback terminals at a node, and configured to receive a highest temperature signal through the node, to obtain a hiqhest temperature value of the plurality of power staqe circuits according to the highest temperature signal, wherein the plurality of power staqe circuits are configured to output a plurality of current feedback signals to the control circuit through the plurality of current feedback terminals; wherein in response to at least one failure event of at least one of the plurality of power staqe circuits, the at least one of the plurality of power staqe circuits controls the hiqhest temperature signal to be in a preset voltaqe level, and outputs at least correspondinq one of the plurality of current feedback signals, which comprises at least one failure code signal, to the control circuit throuqh at least correspondinq one of the plurality of current feedback terminals, and wherein the at least one failure code signal comprises a corresponding pulse count or data code capable of indicatinq the at least one failure event of the at least one of the plurality of power staqe circuits” In particular, Applicants assert that the prior art allegedly fails to disclose “None of the power width modulation, the status information signal 125, and the notification (150) is a signal which is output by power convertor 161, 162 or 163 and further comprises a corresponding pulse count or data code capable of indicating a fault condition of the corresponding power convertor” as argued on page 18 of the remarks.
As an initial matter, the Office agrees that Domingo does disclose the process of detecting a power failure condition, in which the power converters may be fed a feedback control signal, for example signals 105, 106, 107, such that said signals control the output voltage generated by said power converters. However, The Office disagrees with Applicant assertion that there isn’t any notification signal that emanates from the power converters and that the notification signal does not include an encoding mechanism. To the contrary, at least Fig 2 clearly illustrates the status notification signal 125 to be an output from each of the plurality converters. Furthermore, Domingo explicitly discloses how a notification signal, which includes notification signal 125 may be “encoded” to include at least the identity of the power converters that are “experiencing the event” fault caused by the power converters. ¶s [007], [0044]
For at least these reasons, the cited prior art clearly discloses the claimed invention as recited by independent claim 7.
For at least the above reasons the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov