DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 9, and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rasmus et al. (US 2019/0173440).
In regard to Claim 1:
Rasmus discloses, in Figure 2, an amplifier, comprising:
a first differential input pair (M1, M2), comprising a first non-inverting input terminal (inp) and a first inverting input terminal (Inn), and configured to amplify a voltage difference between the first non-inverting input terminal (inp) and the first inverting input terminal (inn) in order to generate a non-inverting output voltage (snp) and an inverting output voltage (snn) of the amplifier (¶ 0016);
a reset circuit (105, 110, M5, M6), coupled to the first differential input pair (M1, M2), and configured to reset the non-inverting output voltage (snp) and the inverting output voltage (snn) of the amplifier according to a reference voltage (Vdd, ¶ 0019);
a first compensation circuit (C8), configured to provide a first compensation voltage to the first non-inverting input terminal (inp), wherein the first compensation voltage is positively correlated with the non-inverting output voltage (snp, ¶ 0021); and
a second compensation circuit (C7), configured to provide a second compensation voltage to the first inverting input terminal (inn), wherein the second compensation voltage is positively correlated with the inverting output voltage (snn, ¶ 0021).
In regard to Claim 2:
Rasmus discloses, in Figure 2, the amplifier of claim 1, further comprising:
a non-inverting output terminal (M2 out), configured to output the non-inverting output voltage (snp); and
an inverting output terminal (M1 out), configured to output the inverting output voltage (snn), wherein the first compensation circuit comprises a first capacitor (C8),
wherein the first capacitor (C8) is coupled between the first non-inverting input terminal (inp) and the non-inverting output terminal (M2 out),
wherein the second compensation circuit comprises a second capacitor (C7),
wherein the second capacitor (C7) is coupled between the first inverting input terminal (inn) and the inverting output terminal (M1 out).
In regard to Claim 9:
Rasmus discloses, in Figure 2, an amplifier, comprising:
a first differential input pair (M1, M2), comprising a first non-inverting input wire (inp) and a first inverting input wire (inn), and configured to amplify a voltage difference between the first non-inverting input wire and the first inverting input wire in order to generate a non-inverting output voltage (snp) and an inverting output voltage (snn) of the amplifier (¶ 0019);
a reset circuit (105, 110, M5, M6), coupled to the first differential input pair (M1, M2), and configured to reset the non-inverting output voltage (snp) and the inverting output voltage (snn) of the amplifier according to a reference voltage (Vdd, ¶ 0019);
a non-inverting output wire (snp wire), configured to transmit the non-inverting output voltage (snp), wherein a portion of the non-inverting output wire is disposed adjacent to the first non-inverting input wire (inp) to form a first compensation capacitor (C8) with the first non-inverting input wire (inp), wherein the first compensation capacitor (C8) is configured to provide a first compensation voltage positively correlated with the non-inverting output voltage (snp) to the first non-inverting input wire (inp); and
an inverting output wire (snn wire), configured to transmit the inverting output voltage (snn), wherein a portion of the inverting output wire is disposed adjacent to the first inverting input wire (inn) to form a second compensation capacitor (C7) with the first inverting input wire (inn), wherein the second compensation capacitor (C7) is configured to provide a second compensation voltage positively correlated with the inverting output voltage (snn) to the first inverting input wire (inn).
In regard to Claim 13:
Rasmus discloses, in Figure 2, a pipelined analog-to-digital convertor (ADC), comprising a convertor circuitry, wherein the convertor circuitry comprises:
an analog-to-digital convertor (R1-R2, S1, S2);
a digital-to-analog convertor (DAC) (iDAC), configured to convert an output of the ADC (R1-R2, S1, S2);
a subtractor (P3, P4), configured to subtract the output of the DAC (iDC) from an input of the ADC (Vdd); and an amplifier (M1-M4, P1-P2), comprising:
a first differential input pair (M1, M2), comprising a first non-inverting input terminal (inp) and a first inverting input terminal (Inn), and configured to amplify a voltage difference between the first non-inverting input terminal (inp) and the first inverting input terminal (inn) in order to generate a non-inverting output voltage (snp) and an inverting output voltage (snn) of the amplifier (¶ 0016);
a reset circuit (105, 110, M5, M6), coupled to the first differential input pair (M1, M2), and configured to reset the non-inverting output voltage (snp) and the inverting output voltage (snn) of the amplifier according to a reference voltage (Vdd, ¶ 0019);
a first compensation circuit (C8), configured to provide a first compensation voltage to the first non-inverting input terminal (inp), wherein the first compensation voltage is positively correlated with the non-inverting output voltage (snp, ¶ 0021); and
a second compensation circuit (C7), configured to provide a second compensation voltage to the first inverting input terminal (inn), wherein the second compensation voltage is positively correlated with the inverting output voltage (snn, ¶ 0021).
In regard to Claim 14:
Rasmus discloses, in Figure 2, the pipelined ADC of claim 13, wherein amplifier further comprises:
a non-inverting output terminal (M2 out), configured to output the non-inverting output voltage (snp); and
an inverting output terminal (M1 out), configured to output the inverting output voltage (snn), wherein the first compensation circuit comprises a first capacitor (C8),
wherein the first capacitor (C8) is coupled between the first non-inverting input terminal (inp) and the non-inverting output terminal (snp),
wherein the second compensation circuit comprises a second capacitor (C7),
wherein the second capacitor (C7) is coupled between first inverting input terminal (inn) and the inverting output terminal (snn).
Allowable Subject Matter
Claims 3-8, 10-12, and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US 2007/0194850) discloses an operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.
Sun et al. (US 2014/0159807) discloses a slicer circuit including an input differential is configured to amplify an input reference voltage received at a pair of differential input nodes and provide a differential output voltage at a pair of differential output nodes, and a regeneration latch configured to amplify the differential output voltage. A differential offset compensation voltage is applied to the differential output voltage to provide DC-offset cancellation. A differential equalization voltage is applied to the differential output voltage to provide DFE equalization.
Bandyopadhyay (US 2016/0344344) discloses a compensation network is electrically connected between an output node of the op-amp and an input differential pair coupled source/emitter tail-current node. The compensation network can include a capacitor having a relatively low value of capacitance. In this manner, op-amp bandwidth is improved while power consumption is reduced to meet a “green” standard.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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