Prosecution Insights
Last updated: April 19, 2026
Application No. 18/602,173

REGULATOR AND POWER MANAGEMENT INTEGRATED CIRCUIT INCLUDING THE SAME

Non-Final OA §102
Filed
Mar 12, 2024
Examiner
JACKSON, LAKAISHA
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
411 granted / 484 resolved
+16.9% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
507
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
46.8%
+6.8% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 484 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed 03/12/2024, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jiang et al. (“Jiang”, US 2024/0319755). Re claim 17, Jiang teaches [Figs 1-2] a method of operating a power management integrated circuit [124, paragraph 29], comprising: receiving a power-off signal from a processor [104, Fig 1]; dropping a regulation voltage [Vout] to a reference voltage [Vref] using a dynamic voltage scaling (DVS) loop [feedback loop] included in the power management integrated circuit; and turning off a power transistor [Mp] included in the power management integrated circuit based on the regulation voltage dropped to the reference voltage [paragraph 33]. Re claim 18, Jiang teaches sensing whether the regulation voltage corresponds to the reference voltage [paragraph 33]. Re claim 19, Jiang teaches setting the reference voltage as a threshold voltage based on the received power-off signal [reference is set by the processor, paragraph 26]. Allowable Subject Matter Claims 1-16 are allowed. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose: Re claim 1 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a reference voltage generation circuit configured to generate a second reference voltage varied from a first reference voltage according to a dynamic control signal; and a control circuit configured to receive a power-off signal from a processor and further configured to turn off the power transistor when the regulation voltage drops to the second reference voltage by the DVS circuit” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 10 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a control circuit configured to control the one or more regulators, wherein the control circuit is configured to operate a dynamic voltage scaling (DVS) loop that drops the regulation voltage to a reference voltage varying according to a dynamic control signal when a power-off signal is provided from a processor and turns off one or more power transistors included in the one or more regulators when the regulation voltage drops to the reference voltage” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 20 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “regulating the regulation voltage based on a first discharge rate until the regulation voltage drops to the reference voltage; and regulating the regulation voltage dropped to the reference voltage based on a second discharge rate lower than the first discharge rate after the regulation voltage drops to the reference voltage” in combination with the additionally claimed features, as are claimed by Applicant. Conclusion Examiner's Note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LaKaisha Jackson/ Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Mar 12, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §102
Feb 24, 2026
Applicant Interview (Telephonic)
Feb 24, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD FOR SUPPLYING A DC LOAD, ENERGY CONVERSION SYSTEM AND ELECTROLYSIS SYSTEM
2y 5m to grant Granted Feb 17, 2026
Patent 12549015
SENSORLESS CURRENT SHARING FOR POWER CONVERTERS
2y 5m to grant Granted Feb 10, 2026
Patent 12549083
POWER CONVERSION SYSTEM FOR LIMITING THE INPUT BURST CURRENT
2y 5m to grant Granted Feb 10, 2026
Patent 12542490
POWER SUPPLY SYSTEM HAVING AUXILIARY WINDING AND BLOCKING MODULE
2y 5m to grant Granted Feb 03, 2026
Patent 12541217
POWER MANAGEMENT DEVICE AND METHOD OF OPERATING THE SAME
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 484 resolved cases by this examiner. Grant probability derived from career allow rate.

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