Prosecution Insights
Last updated: October 02, 2026
Application No. 18/602,329

TRACKER MODULE, POWER SUPPLY SYSTEM, RADIO FREQUENCY SYSTEM, COMMUNICATION DEVICE, AND IC CHIP

Non-Final OA §103
Filed
Mar 12, 2024
Priority
Mar 17, 2023 — JP 2023-043564
Examiner
CHOE, HENRY
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1261 granted / 1368 resolved
+32.2% vs TC avg
Minimal -2% lift
Without
With
+-1.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
26 currently pending
Career history
1373
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
38.8%
-1.2% vs TC avg
§102
46.8%
+6.8% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1368 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4, 8, 11-14, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over [Garrett et al (Fig. 1B); 12,160,208] in view of [Li et al (Fig. 1); 9,037,102]. Regarding claims 1 and 14, Garrett et al discloses an amplifier circuit comprising at least one capacitor (C1-C3) included in a switched capacitor circuit (34) which is configured to generate a plurality of discrete voltages (V1-V3) based on an input voltage (VIN), an IC chip (Fig. 1B) including at least one switch (S0-S3) included in the switched capacitor circuit (34), and at least one switch (Sm1-Sm3) included in a supply modulator (36) which is configured to selectively output at least one (V1 or V2 or V3) of the plurality of discrete voltages (V1-V3) to a power amplifier (40) and wherein the at least one capacitor (C1-C3) is stacked on the IC chip (Fig. 1B). As described above, Garrett et al discloses all the limitations in claim 1 except for that a board and wherein the IC chip disposed on the board. Li et al discloses an integrated circuit (Fig. 1) being disposed on the board (100). The board construction is well-known means for mounting and connecting electronic devices to form an Integrated Circuit (IC). Therefore, it would have been obvious to have integrated the IC chip of Garrett et al on the board, such as taught by Li et al because such a modification would have considered a mere application of well-known conventional board construction. Regarding claims 4 and 17, wherein the at least one capacitor (C1-C3) includes at least one flying capacitor which overlaps the IC chip (Fig. 1B) in a plan view in a thickness direction of the board. Regarding claims 8 and 19, wherein the at least one capacitor (C1-C3) includes at least one smoothing capacitor that overlaps the IC chip (Fig. 1B) in a plan view in a thickness direction of the board. Regarding claim 11, wherein the power amplifier (40) connected to the tracker module (34, 36). Regarding claim 12, wherein a signal processing circuit (34, 36, 38) connected to the RF system (32). Regarding claim 13, Garrett et al discloses an amplifier circuit comprising at least one capacitor (C1-C3) included in a switched capacitor circuit (34) which is configured to generate a plurality of discrete voltages (V1-V3) based on an input voltage (VIN), an IC chip (30) located between the at least one capacitor (C1-C3) and the board (100) and the IC chip (30) including at least one switch (S1-S3) included in the switched capacitor circuit (34) and at least one switch (Sm1-Sm3) included in a supply modulator (36) which is configured to selectively output at least one (V1 or V2 or V3) of the plurality of discrete voltages (V1-V3) to a power amplifier (40). As described above, Garrett et al discloses all the limitations in claim 1 except for that a board and wherein the IC chip disposed on the board. Li et al discloses an integrated circuit (Fig. 1) being disposed on the board (100). The board construction is well-known means for mounting and connecting electronic devices to form an Integrated Circuit (IC). Therefore, it would have been obvious to have integrated the IC chip of Garrett et al on the board, such as taught by Li et al because such a modification would have considered a mere application of well-known conventional board construction. Allowable Subject Matter Claims 2, 3, 5-7, 9, 10, 15, 16, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 9,948,240 teaches an amplifier circuit with a switched capacitor circuit. 2015/0155895 also teaches an amplifier circuit with a switched capacitor circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2976
Read full office action

Prosecution Timeline

Mar 12, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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RF CIRCUIT FOR PREVENTING DAMAGE TO POWER AMPLIFIER
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Patent 12750019
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Patent 12744496
THERMAL DROOP COMPENSATION IN POWER AMPLIFIERS
2y 10m to grant Granted Sep 22, 2026
Patent 12738903
VOLTAGE-TO-TIME-TO-VOLTAGE AMPLIFIER (VTVA) USING TIME DELAY
3y 0m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
90%
With Interview (-1.7%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1368 resolved cases by this examiner. Grant probability derived from career allowance rate.

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