Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reminder of MPEP 2153.01(a)
A disclosure made within the grace period is not prior art under AIA 35 U.S.C. 102(a)(1) if it is apparent from the disclosure itself that it is an inventor-originated disclosure. Specifically, Office personnel may not apply a disclosure as prior art under AIA 35 U.S.C. 102(a)(1) if the disclosure: (1) was made one year or less before the effective filing date of the claimed invention; (2) names the inventor or a joint inventor as an author or an inventor; and (3) does not name additional persons as authors on a printed publication or joint inventors on a patent. This means that in circumstances where an application names additional persons as joint inventors relative to the persons named as authors in the publication (e.g., the application names as joint inventors A, B, and C, and the publication names as authors A and B), and the publication is one year or less before the effective filing date, it is apparent that the disclosure is a grace period inventor disclosure, and the publication is not prior art under AIA 35 U.S.C. 102(a)(1). If, however, the application names fewer joint inventors than a publication (e.g., the application names as joint inventors A and B, and the publication names as authors A, B and C), it would not be readily apparent from the publication that it is an inventor-originated disclosure and the publication would be treated as prior art under AIA 35 U.S.C. 102(a)(1) unless there is evidence of record that an exception under AIA 35 U.S.C. 102(b)(1) applies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et. al, “DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions”.
Regarding Claim 1, Lee et. al teaches a method of training an artificial intelligence model by using a hardware accelerator (Lee et. al, pg. 2, Section II, “The proposed BDPS [Dynamic Block Size and Precision] core in this paper accelerates the DNN [Deep Neural Network] training”), the method comprising: obtaining a training dataset comprising a plurality of first block floating-point values having a first block size (Lee et. al, pg. 2, Section I, “Implement the DBPS core that … performs BFP-based GEMM [generic matrix multiplication] at various block sizes and precisions”); performing a training operation on the artificial intelligence model, based on the training dataset (Lee et. al, pg. 1, Section I, where training DNNs consists of computing the loss of a given input dataset, compute the local gradient, and update the weights based on the computed loss); repeating the training operation on the artificial intelligence model (Lee et. al, pg. 5, Section IV-B, “the host CPU to determine the block size and precision for the next training iterations” describes a new block size for the next iterations) for a predefined number of epochs (Lee et. al, pg. 5, Section V-A, “As the training is noisier with a larger learning rate, we keep the block size small at the beginning then double the block size whenever the learning rate decay happens (e.g., every 20 epochs)”); and reconstructing the training dataset (Lee et. al, pg. 1, Section I, training DNNs consists of a weight update) with a plurality of second block floating-point values having a second block size (Lee et. al, pg. 5, Section IV-B, “the host CPU to determine the block size and precision for the next training iterations” describes a new block size for the next iterations).
Regarding Claim 2, Lee et. al teaches the method of claim 1 (and thus the rejection of Claim 1 is incorporated). Lee teaches the method of claim 1, further comprising: performing the training operation based on the reconstructed training dataset (Lee et. al, pg. 1, Section I, where training DNNs consists of computing the loss of a given input data, compute the local gradient, and update the weights based on the loss); and repeating the training operation on the artificial intelligence model for the predefined number of epochs (Lee et. al, pg. 5, Section V-A, “As the training is noisier with a larger learning rate, we keep the block size small at the beginning then double the block size whenever the learning rate decay happens (e.g., every 20 epochs)”).
Regarding Claim 3, Lee et. al teaches the method of claim 1 (and thus the rejection of Claim 1 is incorporated). Lee further teaches wherein the performing of the training operation on the artificial intelligence model, based on the training dataset, (Lee et. al, pg. 1, Section I, where training DNNs consists of computing the loss of a given input data, compute the gradient, and update the weights based on the loss) comprises: performing, in a first epoch from among the predetermined number of epochs (Lee et. al, pg. 5, Section IV-B, Fig. 8, training operation is repeated for a set plurality of epochs specified for the training operation), the training operation on a first layer of the artificial intelligence model (Lee et. al, pg. 2, Section I, “We implement the DBPS core that actually performs BFP-based GEMM at various block sizes and precisions”), based on a first batch comprising a predefined number of mini-batches out of the training dataset (Lee et. al, pg. 5, Section V-A, “determines the next BFP precision at every 100 training mini batches (fine-grained control)”), the first batch having first precision (Lee et. al, pg. 5, Section IV-B, “the host CPU to determine the block size and precision for the next training iterations”, describing an instance of the “first” precision before the CPU determined a new block size for the next iterations); converting a training operation result in a floating-point format for the first batch into a block floating-point format (Lee et. al, pg. 4, Section IV-A, Fig. 6, the output of the MAC operations leads to the FP2BFP convertor to obtain BFP data); determining second precision of a second batch comprising the predefined number of mini-batches out of the training dataset, based on the converted training operation result (Lee et. al, pg. 5, Section V-A, “determines the next BFP precision at every 100 training mini batches (fine-grained control)”); and performing, in the first epoch, the training operation on the first layer, based on the second batch (Lee et. al, pg. 2, Section I, “We implement the DBPS core that actually performs BFP-based generalized matrix multiplication at various block sizes and precisions.”).
Regarding Claim 4, Lee et. al teaches the method of claim 3 (and thus the rejection of Claim 3 is incorporated). Lee et. al further teaches, wherein the determining of the second precision of the second batch comprising the predefined number of mini-batches out of the training dataset (Lee et. al, pg. 5, Section IV-B, “The underflow count is returned to the RISC-V core that determines the next BFP precision at every 100 training mini batches (fine-grained control).”), based on the converted training operation result (Lee et. al, pg. 5, Section IV-B, “the FP2BFP converter extracts the maximum exponent of a set of outputs”, where the FP2BFP is at the tail end of the training accelerator in the architecture of the BDPS core (Fig. 6)), comprises: determining a number of underflow occurrences for the converted training operation result; and determining the second precision based on the determined number of underflow occurrences (Lee et. al, pg. 5, Section IV-B, “the number of underflows that is counted in the FP2BFP converter in the DBPS core will be used by the host CPU to determine the precision for the next training iterations”).
Regarding Claim 5, Lee et. al teaches the method of claim 4 (and thus the rejection of Claim 4 is incorporated), wherein the determining of the second precision based on the determined number of underflow occurrences comprises: determining whether the determined number of underflow occurrences is greater than a first critical number; and determining the second precision to be higher than the first precision, in response to determining that the determined number of underflow occurrences is greater than the first critical number (Lee et. al, pg. 5, Section V-A, “In the proposed DBPS, we utilize a hysteresis controller that reduces (or increases) the precision when the underflow ratio is below the lower threshold, th− (or above the upper threshold, th+)”).
Regarding Claim 6, Lee et. al teaches the method of claim 4 (and thus the rejection of Claim 4 is incorporated), wherein the determining of the second precision based on the determined number of underflow occurrences comprises: determining whether the determined number of underflow occurrences is less than a second critical number; and determining the second precision to be lower than the first precision, in response to determining that the determined number of underflow occurrences is less than the first critical number (Lee et. al, pg. 5, Section V-A, “In the proposed DBPS, we utilize a hysteresis controller that reduces (or increases) the precision when the underflow ratio is below the lower threshold, th− (or above the upper threshold, th+)”).
Regarding Claim 7, Lee et. al teaches the method of claim 1 (and thus the rejection of Claim 1 is incorporated), wherein the performing of the training operation on the artificial intelligence model, based on the training dataset, comprises performing a multiplication operation between a first tensor corresponding to the training dataset and a second tensor corresponding to a weight value of the artificial intelligence model (Lee et. al, pg. 3, Section IV-A, the inputs of the multiplication operation in Fig. 6 are represented by “X8W4, X8 means 8-bit mantissa for inputs and W4 refers to 4-bit mantissa for weights.” With pg. 4, Section IV-B, “the precision of each tensor (e.g., X and W) demonstrating X and Y to be interpreted as tensors).
Regarding Claim 8, Lee et. al teaches the method of claim 7 (and thus the rejection of Claim 7 is incorporated), wherein the performing of the multiplication operation comprises: performing an exponent multiplication operation between a shared exponent of the first tensor and a shared exponent of the second tensor (Lee et. al, pg. 1, Section I, MAC operations for two shared exponents of two sub tensor blocks are handled); performing a multiply and accumulation (MAC) operation between a sign and a mantissa of the first tensor and a sign and a mantissa of the second tensor (Lee et. al, pg. 1, Section I, “MAC operations for mantissas are performed”); and obtaining a result value of the multiplication operation in a floating-point format, based on the exponent multiplication operation and the MAC operation (Lee et. al, pg. 4, Section IV-A, In a disclosure of the DBPS core architecture in Fig. 6 Lee et. al teaches, “When computing the partial sum, an FP32 adder tree is used”).
Regarding Claim 9, Lee et. al teaches the method of claim 7 (and thus the rejection of Claim 7 is incorporated), wherein the performing of the training operation on the artificial intelligence model, based on the training dataset (Lee et. al, pg. 1, Abstract, “To make the BFP-based training more feasible, we propose dynamic block size and precision scaling (DBPS) for highly efficient DNN training”), comprises converting a result value of the multiplication operation into a block floating-point format (Lee et. al, pg. 4, Section IV-A, Fig. 6, DBPS architecture teaches the output of the multiplication operation in Fig. 6 is followed by a FP2BFP, with pg. 4, Section IV-A, in teaching the pipeline of the DBPS core, “Finally, the FP2BFP converter extracts the maximum exponent of a set of outputs that needs to be blocked together with a given block size for the computations in the next DNN layer”).
Regarding Claim 10, Lee et. al teaches the method of claim 7 (and thus the rejection of Claim 7 is incorporated), wherein precision of the first tensor is different from precision of the second tensor (Lee et. al, pg. 5, Section IV-B, “the FP2BFP converter in the DBPS core will be used by the host CPU to determine the block size and precision for the next training iterations”).
Claims 11-19 recite an electronic device comprising: a memory storing at least one instruction; and at least one processor configured to execute the at least one instruction to: perform precisely the method of claims 1-9 respectively. As Lee et. al performs their method on an accelerator having memory and a processor (Lee et. al, pg. 1 Fig. 1), claims 11-19 are rejected for reasons set forth in the rejections of claims 1-9 respectively. Similarly claim 20 recites a non-transitory computer-readable medium also taught by Lee (Lee et. al, pg. 1, Abstract, “We also present a hardware accelerator, called DBPS core, which supports the DBPS control by configuring arithmetic units with custom instructions extended in a RISC-V processor.”), and is similarity rejected for reasons set forth in the rejection of Claim 1.
Claims 1, 2, 7, 11, 12, 17, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nair et. al, US PG Pub 2019/0042944.
Regarding Claim 1, Nair et. al teaches a method of training an artificial intelligence model (Nair, Abstract, “systems and methods for training a neural network”) by using a hardware accelerator (Nair, [0062], “hardware embodiments of accelerators such as neural net processors”), the method comprising: obtaining a training dataset comprising a plurality of first block floating-point values having a first block size (Nair, Abstract, “training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP 16 values”); performing a training operation on the artificial intelligence model, based on the training dataset (Nair, [0003], “Each epoch includes one forward propagation of data through the neural network and one backward propagation of data through the neural network”); repeating the training operation on the artificial intelligence model for a predefined number of epochs (Nair, [0003], “Training may require numerous epochs to generate reliable and predictable output within an acceptable threshold” where training until the threshold is met is for a predefined number of epochs); and reconstructing the training dataset with a plurality of second block floating-point values having a second block size (Nair, [0030], “the ability to dynamically alter one or more of: the value of the shared exponent 154, the mantissa value of one or more FP16 number, and the exponent value of one or more FP16 number included in the training tensor” where the shared exponent value denotes a size of the block of values in the training tensor & [0083], “means for selecting a first number of bits to represent the variable bit-length mantissa’ is another block size that is dynamically adjusted).
Regarding Claim 2, Nair teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Nair further teaches performing the training operation based on the reconstructed training dataset (Nair, [0030], “the ability to dynamically alter one or more of: the value of the shared exponent 154, the mantissa value of one or more FP16 number, and the exponent value of one or more FP16 number included in the training tensor beneficially permits the processor circuitry 130 to proactively adjust one or more FP16 vales included in the training tensor 200 to avoid potential overflow or underflow conditions during the neural network training process” & [0054], “responsive to a determination that one or more of the 16-bit floating point values will overflow or underflow during a future training epoch, the processor circuitry 130 dynamically alters the value of the shared exponent 154, the mantissa value of one or more FP16 number” denotes that the training will occur based on the adjusted tensor); and repeating the training operation on the artificial neural network for the predefined number of epochs (Nair, [0003], “Training may require numerous epochs to generate reliable and predictable output within an acceptable threshold” where training until the threshold is met is for a predefined number of epochs).
Claims 11 and 12 recite an electronic device comprising: a memory storing at least one instruction; and at least one processor configured to execute the at least one instruction to: perform precisely the method of claims 1 and 2 respectively. As Nair performs their method on an accelerator having memory and a processor (Nair, Fig. 1), Claims 11 and 12 are rejected for reasons set forth in the rejections of claims 1 and 2 respectively. Similarly Claim 20 recites a non-transitory computer-readable medium (Nair, Fig. 1, element 710) to perform the method of Claim 1, and is thus rejected for reasons set forth in the rejection of Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-5 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Nair, US PG Pub 2019/0042944, in view of Annau, US PG Pub 2020/0218982.
Regarding Claim 3, Nair teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Nair further teaches performing, in a first epoch among the predetermined number of epochs, the training operation on a first layer of the artificial intelligence model, based on a first batch … the first batch having a first precision (Nair, [0003], “Each epoch includes one forward propagation of data through the neural network and one backward propagation of data through the neural network” denotes a batch) converting a training operation result in a floating point format for the first batch into a block floating-point format; determining a second precision of a second batch comprising the predefined number of mini-batches of the training dataset, based on the converted operation result (Nair, [0053], “the processor circuitry may include predictive circuity and/or comparator circuitry capable of predicting a 16-bit floating point value 152 during future training epochs” where “predicting a 16-bit floating point value” in context is a block-floating point format since we are checking for overflow or underflow; [0053], “detects data indicative of a potential overflow or underflow condition” & [0054], “responsive to a determination that one or more of the 16-bit floating point values 152 will overflow or underflow during a future training epoch, the processor circuitry 130 dynamically alters the value of one or more of the shared exponent 154, one or more FP16 mantissa values, to minimize or eliminate the possibility of an overflow or underflow condition”); and performing …. the training operation on the first layer, based on the second batch (Nair, [0003], “Each epoch includes one forward propagation of data through the neural network and one backward propagation of data through the neural network” & [0054] “future training epoch”).
Nair teaches that the epochs have batch size and mini-batch size of one (Nair, [0003], “Each epoch includes one forward propagation of data through the neural network and one backward propagation of data through the neural network”) but not that an epoch can have multiple batches (e.g. a first batch comprising a predetermined number of mini-batches and a second batch in the epoch). However, Annau, in an analogous art of neural network training with block floating point values, teaches these limitations (Annau, [0005], “For each epoch, the machine learning tool can select, from any remaining examples in the training data, a single example or multiple examples (mini-batch) for processing an iteration”). It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to use batches of greater than one example, as does Annau, in the invention of Nair (thus updating the precision for a second batch of the first epoch, i.e. at each indication of overflow or underflow in Nair). The motivation to do so is that mini-batches are a common method of neural network training.
Regarding Claim 4, the Nair/Annau combination of Claim 3 teaches the method of Claim 3 (and thus the rejection of Claim 3 is incorporated). Nair further teaches determining a number of underflow occurrences for the converted operation result; and determining the second precision based on the determined number of underflow occurrences (Nair, [0053], “detects data indicative of a potential overflow or underflow condition” & [0054], “responsive to a determination that one or more of the 16-bit floating point values 152 will overflow or underflow during a future training epoch, the processor circuitry 130 dynamically alters the value of one or more of the shared exponent 154, one or more FP16 mantissa values, to minimize or eliminate the possibility of an overflow or underflow condition”).
Regarding Claim 5, the Nair/Annau combination of Claim 4 teaches the method of Claim 4 (and thus the rejection of Claim 4 is incorporated). Nair further teaches determining whether the determined number of underflow occurrences is greater than a first critical number; and determining the second precision to be higher than the first precision, in response to determining (Nair, [0053], “detects data indicative of a potential overflow or underflow condition” & [0054], “responsive to a determination that one or more of the 16-bit floating point values 152 will overflow or underflow during a future training epoch, the processor circuitry 130 dynamically alters the value of one or more of the shared exponent 154, one or more FP16 mantissa values, to minimize or eliminate the possibility of an overflow or underflow condition” where “one” is greater than a critical number of zero).
Claims 13-15 recite an electronic device comprising: a memory storing at least one instruction; and at least one processor configured to execute the at least one instruction to: perform precisely the method of claims 3-5 respectively. As Nair performs their method on an accelerator having memory and a processor (Nair, Fig. 1), Claims 13-15 are rejected for reasons set forth in the rejections of claims 3-5 respectively.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nair, in view of Drumond, and further in view of Noh et al., “FlexBlock: A Flexible DNN Training Accelerator with Multi-Mode Block Floating Point Support.”
Regarding Claim 6, the Nair/Drumond combination of Claim 5 teaches the method of Claim 5 (and thus the rejection of Claim 5 is incorporated). The combination does not teach, but Noh teaches, determining whether the determined number of underflow occurrences is less than a second critical number; and determining the second precision to be lower than the first precision, in response to determining that the determined number of underflow occurrences is less than the first critical number (Noh, pg. 11, Fig. 17(a) illustrates two thresholds on ZSEs, i.e. underflows, for determining whether to raise or lower the precision). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a hysteresis controller, as does Noh, to determine the precision of the block floating point of Nair/Drumond. The motivation to do so is “to slowly change the precision” (Noh, pg. 11, 1st column, 1st paragraph) that is, to not have to reconfigure values’ precision/format more often than necessary.
Claim 16 recites an electronic device comprising: a memory storing at least one instruction; and at least one processor configured to execute the at least one instruction to: perform precisely the method of claim 6. As Nair performs their method on an accelerator having memory and a processor (Nair, Fig. 1), Claims 16 is rejected for reasons set forth in the rejection of Claim 6.
Claims 7-10 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nair, US PG Pub 2019/0042944, in view of Drumond et al., “Training DNNs with Hybrid Block Floating Point.”
Regarding Claim 7, Nair teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Nair does not explicitly teach performing a multiplication operation between a first tensor corresponding to the training dataset and a second tensor corresponding to a weight value of the artificial intelligence model (Nair, [0003], “forward propagation” and “neural network” with “weights” only implies multiplication operation), but Drumond, in the analogous art of block-floating point training, explicitly teaches this limitation (Drumond, pg. 2, 1st paragraph, “multiply and accumulate operation” & pg. 6, Fig. 2). It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to multiply weights by inputs, as does Drumond, in the invention of Nair. The motivation to do so is that this is the normal way neural networks operate.
Regarding Claim 8, the Nair/Drumond combination of Claim 7 teaches the method of Claim 7 (and thus the rejection of Claim7 is incorporated). The block-floating point multiplications of Drumond, already incorporated in the Nair/Drumond combination, further teaches performing an exponent multiplication between a shared exponent of the first tensor and a shared exponent of the second tensor; performing a multiply and accumulation (MAC) operation between a sign and a mantissa of the first tensor and a sign and a mantissa of the second tensor; and obtaining a result value of the multiplication operation in a floating-point format, based on the exponent multiplication operation and the MAC operation (Drumond, pg. 4, Eq. (2) and following paragraph).
Regarding Claim 9, the Nair/Drumond combination of Claim 7 teaches the method of Claim 7 (and thus the rejection of Claim7 is incorporated). The block-floating point multiplications of Drumond, already incorporated in the Nair/Drumond combination, further teaches converting a result value of the multiplication operation back into a block floating-point format (Drumond, pg. 6, Fig, 2, “FP to BFP”).
Regarding Claim 10, the Nair/Drumond combination of Claim 7 teaches the method of Claim 7 (and thus the rejection of Claim7 is incorporated). The block-floating point multiplications of Drumond, already incorporated in the Nair/Drumond combination, further teaches wherein precision of the first tensor is different from precision of the second tensor (Drumond, pg. 4, Eq. (2) where the exponents are different between the two tensors).
Claims 17-19 recite an electronic device comprising: a memory storing at least one instruction; and at least one processor configured to execute the at least one instruction to: perform precisely the method of claims 7-9 respectively. As Nair performs their method on an accelerator having memory and a processor (Nair, Fig. 1), Claims 17-19 are rejected for reasons set forth in the rejections of claims 7-9 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: Nurvitadhi et al., 2019/0205746, also teaches a dynamic block-floating point format for neural network training.
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/BRIAN M SMITH/Primary Examiner, Art Unit 2122
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