Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kumar et al [20240160431]
As to claim 1,
Kumar et al [20240160431] teach
An Information Handling System (IHS), comprising:
a controller, wherein the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator [0016: “CPU or processor in a server platform or network interface device to boot from boot code by loading boot code from memory of a management controller, instead of loading the boot code from a flash memory. FIG. 2 depicts an example of boot image loading from a memory of a management controller by a system.” and 0018; “boot controller 203 can be implemented using a CPU core or a thread of a multi-threaded core. Boot controller 203 can load boot firmware image 222 from memory 212 of management controller 210.” – booting instantiates And 0017: “management controller 210 can be implemented as one or more of: Board Management Controller (BMC), Intel® Management or Manageability Engine (ME), or other devices.”]; and
a plurality of devices coupled to the controller[0017: “Management controller 210 can perform management and monitoring capabilities for system administrators to monitor operation at least of host 200 and devices connected thereto, such as, network interface device 250 and storage device 260, using channels, including channels that can communicate data (e.g., in-band channels) and out-of-band channels. ”], wherein each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework [0043: “an administrator or orchestrator can provide microcode capsule along with meta-data to the management controller. The management controller can authenticate the meta-data (e.g., target platform information, family, models, versions, etc.) to verify the microcode capsule is to be written to the target platform. ”], and wherein at least a given node is configured to communicate to the orchestrator, telemetry data [0017: “Management controller 210 can perform management and monitoring capabilities for system administrators to monitor operation at least of host 200 and devices connected thereto, such as, network interface device 250 and storage device 260, using channels, including channels that can communicate data (e.g., in-band channels) and out-of-band channels. Out-of-band channels can include packet flows or transmission media that communicate metadata and telemetry and may not communicate data. In some examples, management controller 210 can be implemented as one or more of: Board Management Controller (BMC), Intel® Management or Manageability Engine (ME), or other devices. ”] without any involvement by any Operating System (OS) of the HIS [0044: “the SMM code injection capsule (e.g., a driver) along with meta-data can be provided by an administrator or orchestrator to management controller. Management controller can verify the meta-data associated with the SMM code injection capsule (e.g., target platform information, family, models, versions, etc.) to verify the SMM code injection capsule is to be written to the target platform. If verified, the management controller can copy the SMM code injection capsule to the processor-executed SMM through Memory-Mapped BMC Interface (MMBI), input/output (I/O), or memory interface and trigger an SMI. The SMM can be implemented as a processor-executed operating mode for handling system operations including power management, hardware control, or proprietary designed code. ” and 0050: “the processor can execute the microcode without an OS agent deploying the microcode. During operations 1 and 2, management controller can update an event log with a status of activities, as described earlier.” Also see 0022 ]
As to claim 2
Kumar et al teaches the controller comprises an Embedded Controller (EC) or Baseband Management Controller (BMC) 0017: “management controller 210 can be implemented as one or more of: Board Management Controller (BMC), Intel® Management or Manageability Engine (ME), or other devices.”]
As to claim 3,
Kumar teaches the plurality of devices comprises at least one of: a sensor, a sensor hub, a Central Processing Unit (CPU), a Graphical Processing Unit (GPU), an audio Digital Signal Processor (aDSP), a Neural Processing Unit (NPU), a Tensor Processing Unit (TSU), a Neural Network Processor (NNP), an Intelligence Processing Unit (IPU), an Image Signal Processor (ISP), or a Video Processing Unit (VPU), a camera controller, an audio controller, a memory, a Universal Serial Bus (USB) device, a Peripheral Component Interconnect express (PCIe) device, or a Trusted Platform Module (TPM) [0054:” System 900 includes processor 910, which provides processing, operation management, and execution of instructions for system 900. Processor 910 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), XPU, processing core, or other processing hardware to provide processing for system 900, or a combination of processors. An XPU can include one or more of: a CPU, a graphics processing unit (GPU), general purpose GPU (GPGPU), and/or other processing units (e.g., accelerators or programmable or fixed function FPGAs). Processor 910 controls the overall operation of system 900, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.”].
As to claim 4,
Kumar teaches at least one of the plurality of devices is coupled to the controller via at least one of: a Systems-on-Chip (SoC) interconnect, a Peripheral Component Interconnect Express (PCIe) bus, or a Universal Serial Bus (USB) port [0018: “Interface 230 can provide communication using one or more of the following protocols: Improved Inter Integrated Circuit (I3C), Universal Serial Bus Type-C (USB-C), serial peripheral interface (SPI), enhanced SPI (eSPI), System Management Bus (SMBus), I2C, MIPI I3C®, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL). See, for example, Peripheral Component Interconnect Express (PCIe) Base Specification 1.0 (2002), as well as earlier versions, later versions, and variations thereof. See, for example, Compute Express Link (CXL) Specification revision 2.0, version 0.7 (2019), as well as earlier versions, later versions, and variations thereof.”].
As to claim 5,
Kumar et al taches the SoC interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus [0065; “ system 900 can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed interconnects can be used based on: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, Compute Express Link (CXL), high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Infinity Fabric (IF), Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data can be copied or stored to virtualized storage nodes or accessed using a protocol such as NVMe over Fabrics (NVMe-oF) or NVMe (e.g., a non-volatile memory express (NVMe) device can operate in a manner consistent with the Non-Volatile Memory Express (NVMe) Specification, revision 1.3c, published on May 24, 2018 (“NVMe specification”) or derivatives or variations thereof).”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clarke [20190007341], in view of Kumar et al [20240160431]
As to claim 15,
Clarke [20190007341] teaches method, comprising:
producing, via a controller within an Information Handling System (IHS), an orchestrator of a firmware framework [0005: “The first resource node can comprise a first baseboard management controller (BMC) and a first resource. The method can further comprise detecting, by the first fabric controller, a plurality of fabric controllers communicatively coupled to the first fabric controller and forming at least a portion of a fabric attached architecture. Respective fabric controllers of the plurality of fabric controllers can be associated with respective resource nodes” and 113: “Resource node data 834 can comprise data (e.g., firmware) for successfully interfacing with a variety of types, families, generations, and/or versions of resource node products. ” and 109: set for different firmware is loaded which is a framework ] ;
and producing, via a plurality of devices coupled to the controller, a plurality of nodes 0036: “A plurality of fabric controllers can be connected to a plurality of resource nodes to form a fabric attached architecture in accordance with some embodiments of the present disclosure. ” and 0035: “Fabric controller 200 can be, but is not limited to, an embedded computer system, a system on chip (SoC), a system in package (SiP), a single-board computer (SBC), a computer-on-module (COM), a system-on-module (SOM), a single-host controller, or a mutli-host controller. ”, wherein at least a given node is configured to communicate [0050:” Fabric controller 200 can be embedded within, adjacent to, or distant from resource node 212 in various embodiments so long as fabric controller 200 is communicatively coupled to resource node 212 and fabric 250 ”], to the orchestrator, telemetry data without any involvement by any Operating System (OS) of the IHS.
However, does not explicitly teach producing telemetry data without any involvement by any Operating System (OS) of the IHS.
However, Kumar teaches producing telemetry data without any involvement by any Operating System (OS) of the HIS [ [ 0017: “system administrators to monitor operation at least of host 200 and devices connected thereto, such as, network interface device 250 and storage device 260, using channels, including channels that can communicate data (e.g., in-band channels) and out-of-band channels. Out-of-band channels can include packet flows or transmission media that communicate metadata and telemetry” and 0044: “the SMM code injection capsule (e.g., a driver) along with meta-data can be provided by an administrator or orchestrator to management controller. Management controller can verify the meta-data associated with the SMM code injection capsule (e.g., target platform information, family, models, versions, etc.) to verify the SMM code injection capsule is to be written to the target platform. If verified, the management controller can copy the SMM code injection capsule to the processor-executed SMM through Memory-Mapped BMC Interface (MMBI), input/output (I/O), or memory interface and trigger an SMI. The SMM can be implemented as a processor-executed operating mode for handling system operations including power management, hardware control, or proprietary designed code. ” and 0050: “the processor can execute the microcode without an OS agent deploying the microcode. During operations 1 and 2, management controller can update an event log with a status of activities, as described earlier.” And 0053; “ in response to writing to the memory region or register, the processor can execute the microcode without an OS agent deploying the microcode.” And see 0022 ]
It would have been obvious to person of ordinary skill in the art to combine teaching of combination of Clarke and Kumar because both are directed toward managing data and subunits. Furthermore, Kumar improves upon Clarke by being able to transfer data without use of operating system such that the different such that system can perform task without overloading operating system
As to claim 16,
Clarke teaches further comprising: communicating, from the given node to the orchestrator, an indication of an exposed capability and an exposed interface of the given node; receiving, from a requesting node among the plurality of nodes, a request or command to invoke the exposed capabilities of the given node through the exposed interface; and in response to the request, communicating the telemetry data from the given node to the requesting node [0102: “Fabric protocol 832 can comprise the protocol used by a fabric controller for interfacing with a resource node, controlling resources associated with the resource node, generating virtual addresses, providing resource capability information associated with the resource node to a fabric attached architecture, and/or transmitting data throughout the fabric attached architecture. ” and 0034: “Virtualized data-link layer 106 can be used to provide resource capability information associated with various resource nodes to the fabric attached architecture via a control interface of the fabric attached architecture.” And 0049: “Resource capability information can be provided to the fabric 250 by a fabric controller 200 associated with a resource node 212. Resource capability information can indicate performance characteristics (e.g., storage size, processing speed, etc.) available on each resource node 212. Fabric 250 can use resource capability information to utilize appropriate resource nodes 212 as virtual resources. ” and 106: “he 110 devices 812 can include an interface capable of presenting information and receiving input. For example, 110 devices 812 can receive input from a user and present information to a user interacting with fabric manager 800. In some embodiments, fabric manager 800 is connected to the fabric attached architecture 850 via the network interface 815.”].
Allowable Subject Matter
Claim 18-20 allowed.
Kumar [[20240160431]] teaches 0017: “Management controller 210 can perform management and monitoring capabilities for system administrators to monitor operation at least of host 200 and devices connected thereto, such as, network interface device 250 and storage device 260, using channels, including channels that can communicate data (e.g., in-band channels) and out-of-band channels. Out-of-band channels can include packet flows or transmission media that communicate metadata and telemetry and may not communicate data.”
Clark [[20190007341] teaches A plurality of fabric controllers can be connected to a plurality of resource nodes to form a fabric attached architecture in accordance with some embodiments of the present disclosure. ” and 0035: “Fabric controller 200 can be, but is not limited to, an embedded computer system, a system on chip (SoC), a system in package (SiP), a single-board computer (SBC), a computer-on-module (COM), a system-on-module (SOM), a single-host controller, or a mutli-host controller. ”
The prior art of record neither individually nor in combination teach:
produce an orchestrator as part of a firmware framework; and
route telemetry data from a node coupled to the orchestrator to another node coupled to the orchestrator in response to a request or command from the other node to access an exposed capability and interface of the node
Claim 6-14 and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/KESHAB R PANDEY/ Primary Examiner, Art Unit 2176