Prosecution Insights
Last updated: October 27, 2026
Application No. 18/602,545

HEAT DISSIPATION FOR STACKED INTEGRATED CIRCUIT DEVICES

Non-Final OA §102§103
Filed
Mar 12, 2024
Examiner
PAYEN, MARVIN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
367 granted / 474 resolved
+9.4% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
5 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.0%
+21.0% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 474 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 7-13, 15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bartley et al. (2008/0218974, from hereinafter, “Bartley”). Re Claim 1. Bartley discloses in Fig. 2 and [0026]-[0029], an integrated device comprising: a first die (103); a second die (103) stacked above the first die and electrically interconnected to the first die; and a conductive structure (120) in thermal contact with a top surface of the first die and in thermal contact with a top surface of the second die, the conductive structure configured to dissipate heat from the first die and the second die. Re Claim 2. Bartley discloses, wherein the conductive structure includes a thermally conductive foil. Re Claim 3. Bartley discloses, wherein the conductive structure has a ring shape that at least partially encircles the second die. Re Claim 4. Bartley discloses, wherein the conductive structure includes: a first piece (102) attached to the top surface of the first die; and a second piece (102) attached to the top surface of the second die and to the first piece. Re Claim 5. Bartley discloses, wherein the first piece is attached to the second piece via one or more mechanical detents. Re Claim 7. Bartley discloses, wherein the first die is included within a first package, wherein the second die is included within a second package, and wherein the first package and the second package are arranged in a package-on-package (PoP) configuration. Re Claim 8. Bartley discloses, further comprising: a first substrate (106) that is electrically connected to the first die (103); a second substrate (106) that is electrically connected to the second die (103); and electrical interconnects that form signal propagation paths between the first substrate and the second substrate. Re Claim 9. Bartley discloses, wherein the conductive structure includes a conductive element that extends along a pathway between the first substrate and the second substrate that is devoid of the electrical interconnects. Re Claim 10. Bartley discloses, wherein an arrangement of electrical contacts on a bottom surface of the second substrate matches an arrangement of the electrical interconnects. Re Claim 11. Bartley discloses, wherein the electrical interconnects extend from the first substrate to the electrical contacts on the bottom surface of the second substrate to form the signal propagation paths without an intervening interposer substrate. Re Claim 12. Bartley discloses, wherein the conductive structure is in thermal contact with the top surface of the first die via a thermal interface material. Re Claim 13. Bartley discloses, wherein the conductive structure is in thermal contact with the top surface of the second die via a thermal interface material. Re Claim 15. Bartley discloses in Fig. 2 and 0026]-[0029], a method of fabricating a package-on-package (PoP) device, the method comprising: attaching a first portion of a conductive structure to a top surface of a first die; positioning a second die above the first die; and attaching a second portion of the conductive structure to a top surface of the second die. Re Claim 17. Bartley discloses, wherein the first portion is attached to the top surface of the first die via a thermal interface material. Re Claim 18. Bartley discloses, wherein the second portion is attached to the top surface of the second die via a thermal interface material. Re Claim 19. Bartley discloses in Fig. 2 and [0026]-[0029], a device comprising: an integrated device comprising: a first die (103); a second die (103) stacked above the first die and electrically interconnected to the first die; and a first structure (102) in thermal contact with a top surface of the first die and in thermal contact with a top surface of the second die, the first structure configured to dissipate heat from the first die and the second die; a printed circuit board (108) coupled to a bottom surface of the integrated device; and a second structure (102) disposed above the integrated device and in thermal contact with the first structure, the second structure configured to dissipate heat from the device. Re Claim 20. Bartley discloses, wherein the first structure provides a thermal pathway from the first die and the second die to the second structure. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bartley. Re Claim 6. Bartley fails to disclose, wherein the first die includes an application processor, and wherein the second die includes a dynamic random-access memory. However, it is routine and conventional in the art to use different kinds of chips for a particular application or task. Claim 14. Bartley fails to disclose explicitly, further comprising an underfill layer that is disposed between a bottom surface of the second die and the conductive structure. However, using an underfill is conventional and routine in the art. Re Claim 16. Bartley fails to disclose, further comprising: snapping the first portion to the second portion at one or more mechanical detents to form the conductive structure. However, it would have been an obvious matter of design choice to have snap a first portion to the second portion and generally recognized as being within the level of ordinary skill in the art. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARVIN PAYEN whose telephone number is (571)270-7435. The examiner can normally be reached on Monday-Thursday, Fridays off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARVIN PAYEN/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 12, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
80%
With Interview (+2.8%)
2y 10m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 474 resolved cases by this examiner. Grant probability derived from career allowance rate.

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