DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s amendment/response filed on 02/05/2026, which has been entered and made of record. Applicant’s amendments to the Specification and Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed 11/05/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Laine et al. (US 20200051316 A1) in view of Chalfin et al. (US 20210158584 A1, hereinafter “Chalfin”).
Regarding claim 1, Laine discloses A graphics processor that is operable to perform ray tracing, wherein the graphics processor comprises: (para. [0074], “FIG. 1 illustrates an example real time ray interactive tracing graphics system 100 for generating images using three dimensional (3D) data of a scene or object(s)”). Note that: ray interactive tracing graphics system 100 is regarded as a graphics processor.
storage; (FIG. 1: “MEMORY” 140)
a ray tracing circuit operable to trace rays by performing tests to determine whether the rays intersect geometry representing a scene to be rendered, (para. [0060], “In non-limiting embodiments, a hardware co-processor (herein referred to as a "traversal coprocessor" or in some embodiments a "tree traversal unit" or "TTU") accelerates certain processes supporting interactive ray tracing including ray bounding volume intersection tests, ray-primitive intersection tests and ray "instance" transforms”). Note that: traversal coprocessor or TTU is regarded as a ray tracing circuit that accelerate or perform ray-volume and ray primitive tests to determine whether the rays intersect geometry representing the scene for rendering. wherein the ray tracing circuit is operable to use the storage to store test record entries for a ray being traced, wherein each test record entry indicates a test that may need to be performed to trace the ray; and … a number of test record entries that the ray tracing circuit can store in the storage to trace the ray. (para. [0115], “When a ray processes a node using traversal coprocessor 138, it is testing itself against the bounding volumes of the node's children. The ray only pushes stack entries onto its stack for those branches or leaves whose representative bounding volumes were hit. When a ray fetches a node in the example embodiment, it doesn't test against the bounding volume of the node-it tests against the bounding volumes of the node's children. The traversal coprocessor 138 pushes nodes whose bounding volumes are hit by a ray onto the ray's traversal stack in an order determined by ray configuration”). Note that: (1) when a ray processes a root node of the BVH, the traversal coprocessor 138 (the ray tracing circuit) pushes stack entries onto the ray’s traversal stack (storage) for those branches or leaves whose representative bounding volumes were hit; (2) a ray intersection test for each bounding volume of the node in the ray’s stack may need to be performed to trace the ray; (3) the nodes for test in the stack (part of the storage) are regarded as test record entries; and (4) a number of test record entries can be stored by the ray tracing circuit in the storage for ray tracing.
an allocation circuit operable to:
determine whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray; and (para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: (1) a software process or a circuit (stack initializer(s)) responsible for stack initialization or stack memory allocation can be regarded as an allocation circuit; and (2) the co-processor uses short stack traversal and pushes a stack entry that directly references the Primitive Range (leaf type and primitive) on to the top. Since the stack may overflow due to enough stack entries to push, the co-processor can determine whether the stack space is enough for storing or require additional storage space to store test record entries to avoid overflowing the stack.
However, Laine fails to disclose, but in the same art of computer graphics, Chalfin discloses
… when it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace a ray: Note that: if it is determined by the co-processor that the ray tracing circuit (tree traversal unitor TTU) in Laine above may require additional storage space to store test record entries, this time clause is triggered here.
allocate additional storage space from the storage for the ray tracing circuit to use to store test record entries to trace the ray. (Chalfin, para. [0146], “When the current memory block is full, a new, free memory block can then be allocated and linked to the data structure”; para. [0129], “the memory space that is allocated to (and is available to be allocated to) a region comprises memory space from an appropriate pool of free memory space (a "heap") for use by the graphics processor”). Note that: additional free memory is allocated to store test record entries when current memory block is or may be full. , to thereby increase a number of test record entries that the ray tracing circuit can store in the storage to trace the ray. Note that: it is obvious to one having ordinary skills in the art that additional storage space from the storage for the ray tracing circuit can increase the test record entries for ray tracing.
Laine and Chalfin are in the same field of endeavor, namely computer graphics. Before the effective filing date of the claimed invention, it would have been obvious to apply allocating additional or new memory from storage when additional storage may be required, as taught by Chalfin into Laine. The motivation would have been “the technology described herein may therefore allow for an improved (more efficient) usage of memory space and/or improvements in power or performance” (Chalfin, para. [0062]). The suggestion for doing so would allow to improve more efficient usage of memory space and performance. Therefore, it would have been obvious to combine Laine with Chalfin.
Regarding claim 2, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the storage includes an initial storage region reserved for the ray tracing circuit to initially use to store test record entries to trace a ray; and (Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step”; para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: (1) the co-processor uses short stack traversal and pushes or stores a stack entry that directly references the Primitive Range (leaf type and primitive) on to the top; and (2) a small number of stack initializers can initialize the initial storage region(s).
the allocation circuit is operable to:
determine whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray by determining whether the ray tracing circuit may require that more test record entries are stored to trace the ray than can be stored in the initial storage region for the ray; and (Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack); para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: (1) the initialized stack(s) has a determined capability to store a size of test record entries; (2) The co-processor may require more test record entries to push or store in the stack(s); and (3) Since the stack may overflow due to enough stack entries to push, the co-processor can determine whether the stack space is enough for storing or require additional storage space to store test record entries to avoid overflowing the stack.
… when it is determined that the ray tracing circuit may require that more test record entries are stored to trace the ray than can be stored in the initial storage region for the ray. Note that: if it is determined that the co-processor may require more test record entries to push or store in the stack(s) and the stack would overflow because the stack(s) cannot store more entries due to capability, the time clause is triggered.
determine that the ray tracing circuit may require additional storage space to store test record entries to trace a ray… (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: when current stack may be full or overflow for more entries to be pushed or stored, it is determined that the co-processor may require additional storage space to store test record entries to trace a ray.
Regarding claim 3, Laine in view of Chalfin discloses The graphics processor of claim 2, wherein the initial storage region can only store fewer test record entries than a maximum possible number of test record entries that the ray tracing circuit can require are stored to trace a ray. (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: after the initialization to have a stack for beginning the new query, the initial size of the stack is the maximum number of test record entries for the stack to store fewer test record entries than the initial size of the stack before any manipulations to the stack size.
Regarding claim 4, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the ray tracing circuit is operable to trace a group of plural rays together, and the storage includes a shared allocatable storage region reserved for the allocation circuit to allocate for the ray tracing circuit to use to store test record entries to trace any ray of the group of plural rays; and (Laine, para. [0165], “The SM 132 presents one or more rays to the TTU 700 at a time. Each ray the SM 132 presents to the TTU 700 for traversal may include the ray's geometric parameters, traversal state, and the ray's ray flags, mode flags and ray operations information … For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; FIG.23: “Shared Memory/L 1 Cache 1970”). Note that: (1) more rays at a time for TTU to process for ray tracing can be regarded as a group of plural rays; (2) each stack initializer can initialize a specific allocated stack area, region, or a single stack for each ray of the group of rays to store the test record entries for the ray; and (3) Shared Memory/L 1 Cache 1970 can be regarded as a shared allocatable storage region.
(Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack); para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: (1) the initialized stack(s) has a determined capability to store a size of test record entries; (2) The co-processor may require more test record entries to push or store in the stack(s); and (3) Since the stack may overflow due to enough stack entries to push, the co-processor can determine whether the stack space is enough for storing or require additional storage space to store test record entries to avoid overflowing the stack.
the allocation circuit is operable to increase a number of test record entries … by allocating additional storage space from the shared allocatable storage region. (Chalfin, para. [0146], “When the current memory block is full, a new, free memory block can then be allocated and linked to the data structure”; para. [0129], “the memory space that is allocated to (and is available to be allocated to) a region comprises memory space from an appropriate pool of free memory space (a "heap") for use by the graphics processor”). Note that: (1) the co-processor can determine if the ray tracing circuit (tree traversal unitor TTU) in Laine above requires additional storage space to store test record entries; (2) additional free memory is allocated to store test record entries when current memory block is or may be full or it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace a ray; and (3) it is obvious to one having ordinary skills in the art that the allocation circuit can require and allocate additional storage space from the storage for the ray tracing, and increase the test record entries for ray tracing.
The motivation to combine Laine and Chalfin given in claim 1 is incorporated here.
Regarding claim 5, Laine in view of Chalfin discloses The graphics processor of claim 4, wherein the allocation circuit is operable to allocate the allocatable storage region as a whole. (Laine, para. [0115], “it is possible to push nodes onto the traversal stack in the order the nodes appear in memory, or in the order that they appear along the length of the ray, or in some other order”; para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: a small number of stack initializers may initialize or allocate stack as a whole storage region for the ray if the ray in the group of rays is processed at a time.
Regarding claim 6, Laine in view of Chalfin discloses The graphics processor of claim 4, wherein the allocation circuit is operable to allocate parts of the allocatable storage region. (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”). Note that: a small number of stack initializers may initialize or allocate a few stacks as a set of parts of the allocable region for the rays in the group, respectively.
Regarding claim 7, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the allocation circuit is operable to determine whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray by: (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: (1) a software process or a circuit responsible for stack initialization or memory allocation can be regarded as an allocation circuit; and (2) the co-processor uses short stack traversal and pushes a stack entry that directly references the Primitive Range (leaf type and primitive) on to the top; (3) since the stack may overflow due to enough stack entries to push while the stack can only store a determined size of entries, the co-processor can determine whether to require additional storage space to store test record entries to avoid overflowing the stack. .
determining whether a maximum number of test record entries that can be stored for the ray are being stored; and
… when it is determined that a maximum number of test record entries that can be stored for the ray are being stored. (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: (1) after the initialization to have a stack for beginning the new query, the initial size of the stack is the maximum number of test record entries for the stack to store fewer test record entries than the initial size of the stack before any manipulations to the stack size; (2) it is obvious to one having ordinary skills in the art that the co-processor can check the status of the stack(s) regarding the number of stored entries vs. the size of the stacks(s) and determining whether a maximum number of test record entries that can be stored for the ray are being stored; and (3) if it is determined that a maximum number of test record entries that can be stored for the ray are being stored, the time clause is triggered here.
determining that the ray tracing circuit may require additional storage space to store test record entries to trace a ray … (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: when it is determined that a maximum number of test record entries that can be stored for the ray are being stored and current stack may be full or overflow for more entries to be pushed or stored, it is determined that the co-processor may require additional storage space to store test record entries to trace a ray to avoid overflowing the stack.
Regarding claim 8, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the allocation circuit is operable to determine whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray by: (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: (1) a software process or a circuit responsible for stack initialization or memory allocation can be regarded as an allocation circuit; and (2) the co-processor uses short stack traversal and pushes a stack entry that directly references the Primitive Range (leaf type and primitive) on to the top; and (3) since the stack may overflow due to enough stack entries to push while the stack can only store a determined size of entries, the co-processor can determine whether to require additional storage space to store test record entries to avoid overflowing the stack.
determining whether a maximum number of test record entries that can be stored for the ray are being stored;
when it is determined that a maximum number of test record entries that can be stored for the ray are being stored: (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: (1) after the initialization to have a stack for beginning the new query, the initial size of the stack is the maximum number of test record entries for the stack to store fewer test record entries than the initial size of the stack before any manipulations to the stack size; (2) it is obvious to one having ordinary skills in the art that the co-processor can check the status of the stack(s) regarding the number of stored entries vs. the size of the stacks(s) and determining whether a maximum number of test record entries that can be stored for the ray are being stored; and (3) if it is determined that a maximum number of test record entries that can be stored for the ray are being stored, the time clause is triggered here.
determining whether a next operation to be performed by the ray tracing circuit to trace the ray may require that another test record entry is stored for the ray; and (Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”; para. [0090], “The primitive range may be spread out over multiple cache line sized blocks stored in memory. Upon request to test the primitive range for ray-primitive intersections, the blocks are supplied to the traversal coprocessor 138 for processing”; para. [0093], “a primitive range containing a mixture of opaque and alpha primitives spanning multiple blocks regardless of the order that the memory subsystem returns those blocks to the co-processor”). Note that: (1) a primitive range as a volume contains a few primitives; and (2) the co-processor will push a stack entry that can be a primitive range, which means that a next operation (i.e., intersection test between the ray and the volume corresponding to the primitive range) is about to be performed and a stack entry (another test entry) is going to be stored for the ray.
… when it is determined that a next operation to be performed by the ray tracing circuit to trace the ray may require that another test record entry is stored for the ray. Note that: when it is determined by the co-processor that a next operation (i.e., push a stack entry) is about to be performed and a stack entry (another test entry) is stored for the ray, this time clause is triggered here.
determining that the ray tracing circuit may require additional storage space to store test record entries to trace a ray … (Laine, para. [0165], “For some queries, however, a small number of stack initializers may be provided for beginning the new query of a given type”; para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”). Note that: when it is determined that a next operation to be performed by the ray tracing circuit to trace the ray may require that another test record entry is stored for the ray and current stack may be full or overflow for more entries to be pushed or stored, it is determined that the co-processor may require additional storage space to store test record entries to trace a ray to avoid overflowing the stack.
Regarding claim 9, Laine in view of Chalfin discloses The graphics processor of claim 8, wherein the allocation circuit is operable to determine whether a next operation to be performed by the ray tracing circuit to trace the ray may require that another test record entry is stored for the ray by:
determining whether the next operation is a ray-volume intersection test; and (Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”; para. [0090], “The primitive range may be spread out over multiple cache line sized blocks stored in memory. Upon request to test the primitive range for ray-primitive intersections, the blocks are supplied to the traversal coprocessor 138 for processing”; para. [0093], “a primitive range containing a mixture of opaque and alpha primitives spanning multiple blocks regardless of the order that the memory subsystem returns those blocks to the co-processor”). Note that: (1) a primitive range as a volume contains a few primitives; (2) the co-processor will push a stack entry that can be a primitive range, which means that a next operation (e.g., a push operation or intersection test between the ray and the volume corresponding to the primitive range) is about to be performed and a stack entry (another test entry) is going to be stored for the ray; and (3) When the next operation is intersection test between the ray and the volume corresponding to the primitive range, the co-processor determines that the next operation is a intersection test between a ray and a volume (primitive range).
determining that a next operation to be performed by the ray tracing circuit to trace the ray may require that another test record entry is stored for the ray when it is determined that the next operation is a ray-volume intersection test. (Laine, para. [0302], “If the co-processor employs short stack traversal, it will only push a stack entry that directly references the Primitive Range onto the top of the stack or below other leaf nodes pushed onto the top of the stack in the same traversal step. If the query dictated that a Primitive Range should be pushed after one or more I-nodes (whose descendants could potentially push enough stack entries to overflow the stack)”; para. [0090], “The primitive range may be spread out over multiple cache line sized blocks stored in memory. Upon request to test the primitive range for ray-primitive intersections, the blocks are supplied to the traversal coprocessor 138 for processing”; para. [0093], “a primitive range containing a mixture of opaque and alpha primitives spanning multiple blocks regardless of the order that the memory subsystem returns those blocks to the co-processor”). Note that: (1) the co-processor will push a stack entry that can be a primitive range, which means that a next operation (i.e., intersection test between the ray and the volume corresponding to the primitive range) is about to be performed and a stack entry (another test entry) is going to be stored for the ray; and (2) when the co-processor determines that the next operation is an intersection test between a ray and a volume (primitive range), the corresponding stack entry (another test entry) is going to be stored for the ray.
Regarding claim 10, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the allocation circuit is operable to:
determine whether the ray tracing circuit requires that fewer test record entries are stored to trace a ray than can be stored for the ray; and (Laine, para. [0165], “using stack initializers instead of explicit stack initialization improves performance because stack initializers require fewer streaming processor registers and reduce the number of parameters that need to be transmitted from the streaming processor to the TTU”; para. [0115], “When a ray processes a node using traversal coprocessor 138, it is testing itself against the bounding volumes of the node's children. The ray only pushes stack entries onto its stack for those branches or leaves whose representative bounding volumes were hit. When a ray fetches a node in the example embodiment, it doesn't test against the bounding volume of the node-it tests against the bounding volumes of the node's children. The traversal coprocessor 138 pushes nodes whose bounding volumes are hit by a ray onto the ray's traversal stack in an order determined by ray configuration”). Note that: (1) the nodes for test in the stack (part of the storage) are regarded as test record entries; (2) stack initializers define the initial size of the stack(s); (3) it is obvious to one having ordinary skills that TTU can check the status of the stack(s) regarding the number of stored entries and the capability size of the stack(s) and determine whether the number of the stored test record entries in the stack is smaller than the initial size of the stack(s).
when it is determined that the ray tracing circuit requires that fewer test record entries are stored to trace a ray than can be stored for the ray: Note that: if TTU determines that the number of the stored test record entries in the stack is smaller than the initial size of the stack(s), the time clause is triggered here.
deallocate storage space that the ray tracing circuit was using to trace the ray. (Chalfin, para. [0058], “after the primitive data has been used the primitive data can then be released for re-use, and discarded, to free up memory space for new primitive data”). , to thereby reduce a number of test record entries that the ray tracing circuit can store in the storage to trace the ray. Note that: it is obvious to one having ordinary skills in the art that deallocating storage space that the ray tracing circuit was using to trace the ray can result in reducing a number of test record entries.
The motivation to combine Laine and Chalfin given in claim 1 is incorporated here.
Regarding claim 11, Laine in view of Chalfin discloses The graphics processor of claim 1, wherein the ray tracing circuit is operable to use the storage to store a stack of test record entries. (Laine, para. [0115], “When a ray processes a node using traversal coprocessor 138, it is testing itself against the bounding volumes of the node's children. The ray only pushes stack entries onto its stack for those branches or leaves whose representative bounding volumes were hit. When a ray fetches a node in the example embodiment, it doesn't test against the bounding volume of the node-it tests against the bounding volumes of the node's children. The traversal coprocessor 138 pushes nodes whose bounding volumes are hit by a ray onto the ray's traversal stack in an order determined by ray configuration”). Note that: (1) when a ray processes a root node of the BVH, the traversal coprocessor 138 (the ray tracing circuit) pushes stack entries onto the ray’s traversal stack for those branches or leaves whose representative bounding volumes were hit; (2) a ray intersection test for each bounding volume of the node in the ray’s stack may need to be performed to trace the ray; and (3) the nodes for test in the stack (part of the storage) are regarded as test record entries.
Claim 13 reciting “A method of operating” is corresponding to “a graphics processor” of claim 1. Therefore, claim 13 is rejected for the same rationale for claim 1.
In addition, Laine in view of Chalfin discloses A method of operating (Laine, in title, “METHOD FOR HANDLING OF OUT-OF-ORDER OPAQUE AND ALPHA RAY/PRIMITIVE INTERSECTIONS”; para. [0074], “FIG. 1 illustrates an example real time ray interactive tracing graphics system 100 for generating images using three dimensional (3D) data of a scene or object(s)”). Note that: ray interactive tracing graphics system 100 is regarded as a graphics processor.
Claims 14-16 and 17-18 are corresponding to the graphics processor of claims 2-4 and 7-8, respectively. Therefore, claims 14-16 and 17-18 are rejected for the same rationale for claims 2-4 and 7-8, respectively.
Claim 19 is corresponding to the graphics processor of claim 10. Therefore, claim 19 is rejected for the same rationale for claim 10.
Claim 20 reciting “A non-transitory computer readable storage medium storing software code which when executing on a processor performs a method of operating” is corresponding to “a graphics processor” of claim 1. Therefore, claim 13 is rejected for the same rationale for claim 1.
In addition, Laine in view of Chalfin discloses A non-transitory computer readable storage medium storing software code which when executing on a processor performs a method of operating (Laine, “Computer programs, or computer control logic algorithms, may be stored in the main memory 1940 and/or the secondary storage. Such computer programs, when executed, enable the system 1965 to perform various functions. The memory 1940, the storage, and/or any other storage are possible examples of computer-readable media”; FIG. 1: “REAL TIME RAY TRACING RAPHICS SYSTEM”, “PROCESSOR”, “MEMORY”). Note that: memory is non-transitory computer readable storage medium.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Laine in view of Chalfin and Beckmann et al. (US 20220206841 A1, hereinafter “Beckmann”).
Regarding claim 12, Laine in view of Chalfin discloses The graphics processor of claim 11, wherein the storage comprises registers and RAM, (Laine, para. [0325], “records any valid hits in registers or memory accessible by the query's parent thread, and then resubmit the query to resume traversal”)
However, Laine in view of Chalfin fails to disclose, but in the same art of computer graphics, Beckmann discloses and the ray tracing circuit is operable to use the registers to store the top entry of the stack and to use the RAM to store other entries of the stack. (Beckmann, para. [0030], “system 100 executes a ray tracing workload”; para. [0049], “the top of each stack 410 is maintained in register file 420 by spilling the lowest entries of stack 410 to memory (not shown) to make room for new frames pushed onto stack 410”; FIG. 2: ”System Memory 225”, and “GPU 205” including “Memory Controller(s) 220”, “L2 Cache(s)” and “L1 Cache(s)”. Note that: (1) system 100 (the ray tracing circuit) can perform ray tracing; and (2) top entry of the stack is in register file 420 that is a set of registers, while other entries of the stack 410 (e.g., lowest entries and others) can be spilled in memory (e.g., RAM, cache). It is obvious to one having ordinary skill in the field that ”System Memory 225” and “L2 Cache(s)” / “L1 Cache(s)” that can be written and read can be RAMs.
Laine in view of Chalfin, and Beckmann, are in the same field of endeavor, namely computer graphics. Before the effective filing date of the claimed invention, it would have been obvious to apply using the registers to store the top entry of the stack and using the RAM to store other entries of the stack, as taught by Beckmann into Laine in view of Chalfin. The motivation would have been “The control unit has complete flexibility determining how many registers to spill based on dynamic demands and can prefetch the upcoming necessary fills” (Beckmann, Abstract). The suggestion for doing so would allow to flexibly define and create the stack and improve the speed of access of the stack. Therefore, it would have been obvious to combine Laine, Chalfin, and Beckmann.
Response to Arguments
Applicant's arguments with respect to claim rejection 35 U.S.C. 103, have been fully considered but they are not persuasive.
Applicant alleges, “Accordingly, Laine does not disclose, in particular, an allocation circuit that is operable to: determine whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray; and … as now claimed in claim 1. Nor does it disclose a method including determining whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray; and … as defined in claims 11 and 20.” (page 11 / line 21 – page 12 / line 8). However, Examiner respectfully disagrees about the respective allegations as whole because: (1) Applicant makes the statement above but does not provide any rationale for the statement regarding why the limitations are not disclosed by the reference(s); and (2) the detailed reference citations by Laine and explanations have been set forth for the corresponding limitations in claims 1, 11, and 20. The arguments are not persuasive.
Applicant alleges, “However, Chalfin, like Laine, does not disclose or suggest an arrangement in which a number of test record entries that a ray tracing circuit can store in storage to trace a ray can be increased by allocating additional storage space when it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace the ray. Thus, the combination of Chalfin and Laine does not teach or suggest the allocation circuit as defined in claim 1 or a method including determining whether the ray tracing circuit may require additional storage space to store test record entries to trace a ray; and when it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace a ray: allocating additional storage space from the storage for the ray tracing circuit to use to store test record entries to trace the ray, to thereby increase a number of test record entries that the ray tracing circuit can store in the storage to trace the ray", as now claimed in claims 13 and 20. Hence, one of average skill in the art could not find independent claims 1, 13 and 20, and claims Claims 2-11 and 14-19 dependent from claims 1 and 13, obvious.” (page 13, lines 13-25). However, Examiner respectfully disagrees about the respective allegations as whole because: (1) Applicant makes the statement above but does not provide any rationale and clear explanations for the statement regarding why the limitations are not disclosed by the reference(s); (2) regarding “when it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace a ray: allocating additional storage space from the storage for the ray tracing circuit to use to store test record entries to trace the ray, to thereby increase a number of test record entries that the ray tracing circuit can store in the storage to trace the ray", the detailed reference citations by Chalfin and explanations have been set forth for the corresponding limitations in claims 1, 13, and 20 above; (3) The combinations of Laine and Chalfin instead of either Laine or Chalfin discloses all limitations of claims 1, 13, and 20 (see the rationale and detailed citations) above; and (4) claims 2-11 and 14-19 from claims 1 and 13 are rejected for the respective rationale above. The arguments are not persuasive.
Applicant alleges, “Beckmann is cited in combination with Laine and Chalfin for teaching that a ray tracing circuit is operable to use registers to store a top entry of a stack and to use the RAM to store other entries of the stack. However, nothing in Beckmann teaches the method according to claim 11 from which claim 12 depends, including a method such that" ... when it is determined that the ray tracing circuit may require additional storage space to store test record entries to trace a ray: allocating additional storage space from the storage for the ray tracing circuit to use to store test record entries to trace the ray, to thereby increase a number of test record entries that the ray tracing circuit can store in the storage to trace the ray"” (page 14, lines 3-10). However, Examiner respectfully disagrees about the respective allegations as whole because: (1) the combination of Laine and Chalfin discloses all limitations of claim 11 and Beckmann has nothing to do with claim 11; (2) The combinations of Laine, Chalfin, and Beckmann discloses all limitations of claim 12; and (3) the rationale and detailed citation are provided for the rejection of claim 12. The arguments are not persuasive.
Applicant alleges, “Hence, one of average skill in the art could not find claim 13, dependent on independent 11 and 14-19 dependent from claims 1 and 13, obvious.” (page 14, lines 11-12). However, Examiner respectfully disagrees about the respective allegations as whole because: (1) claim 13 is an independent claim; (2) claim 11 is a dependent claim; (3) claims 14-19 depend from claim 13 and not from claim 1; and (4) In any sense, claim 12 is rejected for the rationale and detailed recitations above. The arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Biao Chen/
Patent Examiner, Art Unit 2611
/KEE M TUNG/Supervisory Patent Examiner, Art Unit 2611