DETAILED ACTION
This communication is responsive to the application, filed August 5, 2026. Claims 1-10 and 12-23 are pending in this application. The applicant has canceled claim 11.
Examined under the first inventor to file provisions of the AIA
The present application was filed on March 12, 2024, which is on or after March 16, 2013, and thus is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-10 and 12-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,960,367 B2 in view of Desimone et al. (US 2014/0181339 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of present application are obvious by the claims of issued patent in view of Desimone.
Claims 1-10 and 12-23 are compared to claims 1-20 of US patent US 11,960,367 B2 in view of Desimone in the following table:
Instant Application
US Patent No : US 11,960,367 B2
1. A method of operating a Peripheral Component Interconnect Express (PCIe) device, comprising:
performing a link setting operation of a link including a plurality of lanes;
setting the link to have a link width of the link that includes remaining lanes, except for a fail lane from among the plurality of lanes, based on a result of the link setting operation; and
performing an equalization operation on each of the remaining lanes included in the link width, the equalization operation determining a transmitter or receiver setting of each of the remaining lanes with respect to each of a plurality of EQ coefficients to improve a quality of signals transmitted and received through the remaining lanes.
1. A Peripheral Component Interconnect Express (PCIe) device, comprising:
a plurality of lanes comprising a plurality of ports; a link controller setting a link including the plurality of lanes
wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes
‘367 discloses performing equalization operations, but fails to explicitly disclose for improving quality of signals. Desimone discloses [0064-0081] performing equalization operation on active lanes for improving quality of signals. It would have been obvious to modify ‘367 with Desimone because it allows to improve jitter tolerance and reduce errors.
2. The method of claim 1, wherein the fail lane has a state in which the fail lane is unable to form the link with the remaining lanes that have not failed from among the plurality of lanes.
2. The PCIe device of claim 1, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with the remaining lanes that have not failed from among the plurality of lanes.
3. The method of claim 1, further comprising:
detecting, in response to the link is in a detect state, the fail lane by the link setting operation corresponding to the detect state; and
performing the link setting operation corresponding to the detect state on the remaining lanes.
4. The PCIe device of claim 1, wherein when the link is in a detect state, the link controller detects the fail lane by a link setting operation corresponding to the detect state and performs the link setting operation corresponding to the detect state on the remaining lanes.
4. The method of claim 1, further comprising:
detecting, in response to the link is in a polling state, the fail lane by the link setting operation corresponding to the polling state; and
performing the link setting operation corresponding to the polling state on the remaining lanes.
5. The PCIe device of claim 1, wherein when the link is in a polling state, the link controller detects the fail lane by a link setting operation corresponding to the polling state and performs the link setting operation corresponding to the polling state on the remaining lanes.
5. The method of claim 1, further comprising performing, in response to the link is in a configuration state, the link setting operation corresponding to the configuration state on the remaining lanes.
6. The PCIe device of claim 1, wherein when the link is in a configuration state, the link controller performs a link setting operation corresponding to the configuration state on the remaining lanes.
6. The method of claim 1, wherein the setting of the link comprises:
determining a link number of the link; and
determining lane numbers of the remaining lanes, respectively.
7. The PCIe device of claim 6, wherein the link controller determines a link number of the link and lane numbers of the remaining lanes, respectively, in the configuration state.
7. The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes by a lane number negotiation operation.
8. The PCIe device of claim 7, wherein the link controller determines the lane numbers of the remaining lanes by a lane number negotiation operation.
8. The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes so that the lane numbers increase sequentially.
9. The PCIe device of claim 7, wherein the link controller determines the lane numbers of the remaining lanes so that the lane numbers increase or decrease sequentially.
9. The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes so that the lane numbers increase or decrease sequentially.
9. The PCIe device of claim 7, wherein the link controller determines the lane numbers of the remaining lanes so that the lane numbers increase or decrease sequentially.
10. The method of claim 6,
further comprising providing the link number and the lane numbers of the remaining lanes to a plurality of ports forming the remaining lanes with a plurality of other ports through the plurality of other ports.
9. The PCIe device of claim 7, wherein the link controller determines the lane numbers of the remaining lanes so that the lane numbers increase or decrease sequentially.
10. The PCIe device of claim 7, wherein the plurality of lanes comprises a plurality of other ports and the link controller provides the plurality of other ports with the link number and the lane numbers of the remaining lanes through the plurality of ports.
12. The method of claim 11, further comprising:
determining a final EQ coefficient among the plurality of EQ coefficients based on log information indicating a number of equalization operation attempts with respect to each of the plurality of EQ coefficients and error information about an error occurring in the equalization operation with respect to each of the plurality of EQ coefficients.
1. an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and storing error information about an error occurring in an LO state with respect to each of the plurality of EQ coefficients,
13. The method of claim 12, wherein the error occurs in an L0 state.
1. storing error information about an error occurring in an LO state with respect to each of the plurality of EQ coefficients,
14. The method of claim 12, wherein the error includes at least one of a training sequence error, an ordered set (OS) error, a receiver (RX) error, a decoding error, a sync-header error, and a framing error.
12. The PCIe device of claim 1, wherein the error includes at least one of a training sequence error, an ordered set (OS) error, a receiver (RX) error, a decoding error, a sync-header error, and a framing error.
15. The method of claim 12, further comprising generating the log information with respect to each of the plurality of EQ coefficients based on a result of the equalization operation.
1. an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and
16. The method of claim 12, further comprising generating the error information with respect to each of the plurality of EQ coefficients based on a result of the equalization operation.
1. an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and storing error information
17. The method of claim 12, wherein each of the plurality of EQ coefficients comprises a combination of a pre-cursor, a cursor and a post-cursor.
15. The PCIe device of claim 1, wherein each of the plurality of EQ coefficients includes a combination of a pre-cursor, a cursor and a post-cursor.
18. The method of claim 12, wherein the determining of the final EQ coefficient comprises determining the final EQ coefficient using the log information in response to the number of equalization operation attempts with respect to preset combinations exceeds a first threshold number for the plurality of EQ coefficients.
16. The PCIe device of claim 1, wherein the EQ controller determines the final EQ coefficient using the log information when the number of equalization operation attempts with respect to preset combinations exceeds a first threshold number for the plurality of EQ coefficients.
19. The method of claim 12, wherein the determining of the final EQ coefficient comprises determining the final EQ coefficient using the error information in response to the number of equalization operation attempts with respect to the plurality of EQ coefficients exceeds a second threshold number.
17. The PCIe device of claim 1, wherein the EQ controller determines the final EQ coefficient using the error information when the number of equalization operation attempts with respect to the plurality of EQ coefficients exceeds a second threshold number.
20. The method of claim 12, wherein the determining of the final EQ coefficient comprises determining one of three EQ coefficients, from among the plurality of EQ coefficients having the fewest errors occurring in a unit time, as the final EQ coefficient in response to the number of equalization operation attempts corresponding to each of the three EQ coefficients exceeds a third threshold number.
18. The PCIe device of claim 1, wherein the EQ controller determines one of three EQ coefficients, from among the plurality of EQ coefficients having the fewest errors occurring in a unit time in the LO state, as the final EQ coefficient when the number of equalization operation attempts corresponding to each of the three EQ coefficients exceeds a third threshold number.
21. The method of claim 12, further comprising determining, in response to the link is reset, whether the equalization operation on the external device, which connected to the PCIe device through the link, is performed before the link is reset using port information including a full swing (FS) value.
19. The PCIe device of claim 1, wherein when the link coupled to the PCIe device is reset, the EQ controller determines whether the equalization operation on the external device is performed before the link is reset using port information including a full swing (FS) value or a low frequency (LF) value.
22. The method of claim 12, further comprising determining, in response to the link is reset, whether the equalization operation on the external device, which connected to the PCIe device through the link, is performed before the link is reset using port information including a low frequency (LF) value.
19. The PCIe device of claim 1, wherein when the link coupled to the PCIe device is reset, the EQ controller determines whether the equalization operation on the external device is performed before the link is reset using port information including a full swing (FS) value or a low frequency (LF) value.
23. The method of claim 12, further comprising performing a re-equalization operation for resetting the transmitter or receiver setting of each of the remaining lanes in response to a number of errors occurring in a unit time exceeds a threshold error value.
20. The PCIe device of claim 1, wherein the EQ controller controls the PCIe device to perform a re-equalization operation for resetting the transmitter or receiver setting of each of the plurality of lanes when a number of errors occurring in a unit time in the LO state exceeds a threshold error value.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak et al. (US 2018/0095920 A1) in view of Butcher et al. (US 2016/0170918 A1) and further in view of Desimone et al. (US 2015/0092828 A1).
As per claim 1: A method of operating a Peripheral Component Interconnect Express (PCIe) device, comprising:
performing a link setting operation of a link including a plurality of lanes;
Kwak discloses [0006] in order for PCIe devices to transmit and receive data, an initialization routine for setting a link in a physical layer of the PCIe interface protocol must be executed.
setting the link to have a link width of the link that includes remaining lanes, except for a fail lane from among the plurality of lanes, based on a result of the link setting operation; and
Kwak discloses [Fig. 3; 0032-0034, 0045-0047] detecting a fail lane by the link setting operation and performing link number negotiation for all the lanes. Kwak discloses setting the link width [0056], but fails to explicitly disclose setting the link width that includes remaining lanes except for a fail lane. Butcher discloses a similar method, which further teaches [0032-0040] the lane assigner may assign the second set of lanes, which does not include the degraded lanes (fail lanes), for operation. The second set of lanes may be a contiguous group of lanes or the second set of lanes may include lanes from a first half of the data bus and lanes from the second half of the data bus, but do not include any degraded lanes.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Kwak with that of Butcher. One would have been motivated to set the link width to include remaining lanes and not fail lanes because it allows to perform operations without degraded lanes [Butcher; 0032-0040].
performing an equalization operation on each of the remaining lanes included in the link width,
Kwak and Butcher disclose performing link setting operation and setting the link width that includes remaining lanes except for a fail lane, but fail to explicitly disclose performing an equalization operation on each of the remaining lanes. Desimone discloses a similar method, which further teaches [0077-0081] obtaining the active physical lanes of a negotiated PCIe link, iterating until each lane of the link has been tested, and testing selected transmitter EQs (TxEQs) for each lane.
the equalization operation determining a transmitter or receiver setting of each of the remaining lanes
Desimone discloses [0062-0063; 0134-0135] dynamically adjusting transmitter and receiver equalization settings and specifically identifies a selected transmitter EQ (TxEQ) for the respective lane.
with respect to each of a plurality of EQ coefficients
Desimone discloses [0068-0071] looping through candidate TxEQ coefficients, and explicitly states that any number may be tested, providing examples of one, five, and ten coefficients.
to improve a quality of signals transmitted and received through the remaining lanes.
Desimone discloses [0069-0073; 0093-0099; 0132-0140] selecting the coefficient for each lane that produces the greatest jitter tolerance, evaluates lane performance by errors and BER failure, and retrains the PCIe link using the selected coefficient. To summarize, Desimone teaches [0064-0081] a PCIe equalization procedure in which a plurality of candidate transmitter equalization coefficients are tested for each lane of a communication link, a coefficient yielding the best performance result for each tested lane is selected, and the selected coefficient is applied by retraining the link. The PCIe link may have a plurality of lanes and that the procedure iterates until each lane has been tested.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the PCIe device of Kwak, as modified by Butcher to establish a link using lanes remaining after exclusion of a failed/degraded lane, to perform Desimone’s per-lane equalization procedure on the active remaining lanes. Desimone expressly teaches testing a plurality of TxEQ coefficients for each lane, selecting the coefficient that produces the best lane-performance result, and applying that coefficient through PCIe link retraining. The modification would predictably improve the signal integrity of the active lanes by improving jitter tolerance and reducing errors [Desimone; 0064-0081], while retaining Kwak and Butcher’s ability to establish a usable link that excludes failed lanes.
As per claim 2: The method of claim 1, wherein the fail lane has a state in which the fail lane is unable to form the link with the remaining lanes that have not failed from among the plurality of lanes.
Butcher discloses [0005-0007] bifurcating the degraded lanes and further isolating one or more degraded lanes
As per claim 3: The method of claim 1, further comprising:
detecting, in response to the link is in a detect state, the fail lane by the link setting operation corresponding to the detect state; and
performing the link setting operation corresponding to the detect state on the remaining lanes.
Kwak discloses [Fig. 3; 0032-0034, 0045-0047] detecting a fail lane by the link setting operation and performing link number negotiation for all the lanes.
As per claim 4: The method of claim 1, further comprising:
detecting, in response to the link is in a polling state, the fail lane by the link setting operation corresponding to the polling state; and
performing the link setting operation corresponding to the polling state on the remaining lanes.
Kwak discloses [0032-0034] the LTSSM of the PCIe device detects eleven states, one of them being the polling state and the LTSSM is used to perform various operations corresponding to the polling state on the lanes.
As per claim 5: The method of claim 1, further comprising performing, in response to the link is in a configuration state, the link setting operation corresponding to the configuration state on the remaining lanes.
Kwak discloses [0032-0034] the LTSSM of the PCIe device detects eleven states, one of them being the configuration state and the LTSSM is used to perform various operations corresponding to the configuration state on the lanes.
As per claim 6: The method of claim 1, wherein the setting of the link comprises:
determining a link number of the link; and
determining lane numbers of the remaining lanes, respectively.
Kwak discloses [0047-0056] the PCIe device performs a link number negotiation in order of sequentially increasing the port number of the plurality of ports P0 to P7 of the PCIe interface connector. The ordering of the ports may be a sequential increase from a lowest designated port to a highest designated port. Alternately, an ordering of the ports may be a sequential decreasing from the highest designated port to the lowest designated port.
As per claim 7: The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes by a lane number negotiation operation.
Kwak discloses [0047-0056] the PCIe device performs a link number negotiation in order of sequentially increasing the port number of the plurality of ports P0 to P7 of the PCIe interface connector. The ordering of the ports may be a sequential increase from a lowest designated port to a highest designated port. Alternately, an ordering of the ports may be a sequential decreasing from the highest designated port to the lowest designated port.
As per claim 8: The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes so that the lane numbers increase sequentially.
Kwak discloses [0047-0056] the PCIe device performs a link number negotiation in order of sequentially increasing the port number of the plurality of ports P0 to P7 of the PCIe interface connector. The ordering of the ports may be a sequential increase from a lowest designated port to a highest designated port. Alternately, an ordering of the ports may be a sequential decreasing from the highest designated port to the lowest designated port.
As per claim 9: The method of claim 6, wherein the determining of the lane numbers comprises determining the lane numbers of the remaining lanes so that the lane numbers increase or decrease sequentially.
Kwak discloses [0047-0056] the PCIe device performs a link number negotiation in order of sequentially increasing the port number of the plurality of ports P0 to P7 of the PCIe interface connector. The ordering of the ports may be a sequential increase from a lowest designated port to a highest designated port. Alternately, an ordering of the ports may be a sequential decreasing from the highest designated port to the lowest designated port.
As per claim 10: The method of claim 6, further comprising providing the link number and the lane numbers of the remaining lanes to a plurality of ports forming the remaining lanes with a plurality of other ports through the plurality of other ports.
Kwak discloses [Fig. 2; 0041-0047] providing the link number and the lane numbers to a plurality of ports forming the lanes with a plurality of other ports.
Allowable Subject Matter
Claims 12-23 are objected to as being dependent upon a rejected base claim, but would be allowable if they overcome the Double Patenting rejection above and are rewritten in independent form including all of the limitations of the base claim and any intervening claims. The cited references disclose determining a final EQ coefficient which yielded the best performance results [See Desimone; 0083], but fail to explicitly teach or suggest determining a final EQ coefficient based on log information indicating a number of equalization operation attempts with respect to each of the EQ coefficients and error information about an error occurring in the equalization operation of claim 12. Claims 13-23 depend from claim 12 and would be allowable based on their dependency to claim 12.
Response to Arguments
Applicant's arguments filed August 5, 2026 in regards to the Double Patenting rejection have been fully considered but they are not persuasive. However, based on the amended claims, the examiner has updated the Double Patenting rejection to obviousness type double patenting in view of Desimone.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely solely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
· US 2005/0201454 A1 – Chaudhuri discloses auto-calibration of equalization measuring link loss and automatically determining equalization setting from a look-up table of multiple equalization settings to improve eye margins.
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/JIGAR P PATEL/Primary Examiner, Art Unit 2114
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