Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is in response to the communication filed on 12/22/2025. Claims 1-20 were pending in the application. Claims 12-20 are allowed. Claims 5-6 are objected. Claims 1-4 and 7-11 have been rejected.
Response to Arguments
Applicant’s arguments, see page 8 of remarks filed on 12/22/2025, with respect to the rejections of claims 1-4, 7-8 and 10 under 35 USC 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of BENNETT et al. reference. Upon further examination and consideration, previous 35 USC 102(a)(1) type rejections of claims 12-19 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0319781 A1 (hereinafter Chhabra et al.) in view of US 2022/0123940 A1 (hereinafter BENNETT et al.)
Regarding claim 1, Chhabra et al. teaches a device (note figure 3.300: CPU; para. [0059]: multicore processor; SoC) comprising:
a processor (note figure 3.310: processor core; para. [0059], [0060]: processor); and
a replay protection circuit (note figure 3.346: replay protection logic; figure 3.340: TPM module) coupled to the processor (note figure 3.310: processor core; para. [0060]) and including a memory interface circuit (note figure 3.330: shared cache; figure 3.345: TPM cache; note para. [0042]), wherein the replay protection circuit is configured to generate a message authentication code (MAC) from at least one block of data and too access the at least one of the data via the memory interface circuit (note figure 1.130: memory controller; para. [0063], [0064], [0068]: generation of MAC by integrity validation module inside the TPM module) using ciphertext that is generated by the replay protection circuit in response to a plaintext memory address received from the processor (note para. [0066], [0069]: generating MAC based on encrypted data), wherein the ciphertext comprises a ciphertext memory address that is generated from the plaintext memory address (note para. [0066], [0071]: accessing encrypted memory address)
Chhabra et al. fails to teach expressly wherein the at least one block of data accessed from an external memory at the ciphertext memory address.
However, BENNETT et al. teaches wherein the at least one block of data accessed from an external memory at the ciphertext memory address (note para. [0021], [0045], [0052]: accessing watermarked data from specified/ encrypted memory address)
BENNETT et al. and Chhabra et al. analogous art because they are from the same field of endeavor of preventing unauthorized access to a secure memory region/ element. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in art to modify Chhabra et al device to further include the features of wherein the at least one block of data accessed from an external memory at the ciphertext memory address since such arrangement would provide users with an improved data protection mechanism against side channel/ replay attacks (note BENNETT et al., para. [0021], [0035])
Regarding claim 2, it is rejected applying as same motivation and rationale applied above rejecting claim 1, furthermore, Chhabra et al. teaches the device of claim 1, wherein the replay protection circuit includes a cipher circuit that is configured to generate the ciphertext memory address from the plaintext memory address (note para. [0066], [0071]: generating encrypted memory address)
Regarding claim 3, it is rejected applying as same motivation and rationale applied above rejecting claim 2, furthermore, Chhabra et al. teaches the device wherein the cipher circuit is configured to generate the ciphertext memory address from the plaintext memory address and key that is held in the cipher circuit (note para. [0066], [0071]: storing encrypted memory address)
Regarding claim 4, it is rejected applying as same motivation and rationale applied above rejecting claim 3, furthermore, Chhabra et al. teaches the device wherein the key is hanged upon each power up of the device (note para. [0066], [0071], [0100]: key storage; MAC computation at initialization)
Regarding claim 7, it is rejected applying as same motivation and rationale applied above rejecting claim 1, furthermore, Chhabra et al. teaches the device wherein the replay protection circuit includes a ciphertext circuit that is configured to generate the ciphertext from the plaintext memory address (note para. [0066], [0071]: encrypted memory address)
Regarding claim 8, it is rejected applying as same motivation and rationale applied above rejecting claim 7, furthermore, Chhabra et al. teaches the device wherein the cipher circuit is configured to use a key that is held in the cipher circuit to generate the ciphertext from the plaintext memory address (note para. [0066], [0071]: key storage; encrypted memory address)
Regarding claim 9, it is rejected applying as same motivation and rationale applied above rejecting claim 7, furthermore, Chhabra et al. teaches the device of claim 8, wherein the key is changed upon each power up of the device (note para. [0066], [0071], [0100]: computations of keys and MAC at initialization)
Regarding claim 10, it is rejected applying as same motivation and rationale applied above rejecting claim 7, furthermore, Chhabra et al. teaches the device wherein the replay protection circuit is configured to:
generate multiple ciphertext memory addresses from the plaintext memory addresses (note para. [0066], [0071]: generating encrypted memory address);
access multiple data blocks via the memory interface circuit using the multiple ciphertext memory address (note figure 1.130: memory controller for accessing data); and
generate the MAC using the multiple data blocks (note para. [0066], [0069]: generating MAC based on encrypted data)
Regarding claim 11, it is rejected applying as same motivation and rationale applied above rejecting claim 1, furthermore, BENNETT et al., teaches the device wherein the cipher circuit is configured to use a multiple keys, wherein a key is selected in response to a watermark (note para. [0045], [0048]: using keys and address information to generate watermarked data)
Allowable Subject Matter
Claims 12-20 are allowed.
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/SHANTO ABEDIN/ Primary Examiner, Art Unit 2494