Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 18/603031 has claims 1-20 pending. The effective filing date of this application is 04/13/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 10, 13 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen (2020/0356295) hereinafter Shen.
Regarding claim 1, Shen teaches An apparatus (Shen: Fig. 1: system 100), comprising:
a memory device (Shen: Fig. 1: storage device 104); and
a controller coupled with the memory device and configured to cause the apparatus to (Fig. 1: [0018]: “System 100 comprises a host controller 102 in communication with a storage device 104”):
transfer first data from one or more first source data blocks of a first portion of a memory system to one or more first destination data blocks of a second portion of the memory system according to a first set of parameters used to write the first data to the one or more first destination data blocks, wherein the transfer of the first data is based at least in part on determining that a first quantity of unavailable source data blocks of the first portion of the memory system satisfies a first threshold (Shen: [0001]: “a data storage drive having a first media partition having a first write speed and a second media partition having a second write speed slower than the first write speed “; [0012]: “When a threshold level of storage in the first media partition is reached, transfer is made of that data to a second media partition that has a slower write speed than the first media partition”);
receive, from a host system, one or more commands to write second data to the memory system (Shen: [0015]: “ a host controller sends frequent write commands to, especially when the write command are sent to the address space randomly”);
write the second data to one or more second source data blocks of the first portion of the memory system based at least in part on receiving the one or more commands (Shen: [0017]: “Data to be written to the data storage device, sent from a host controller, is written to the first data storage area media partition until such partition is full or nearly full”); and
transfer third data from one or more third source data blocks of the first portion of the memory system to one or more second destination data blocks of the second portion of the memory system according to a second set of parameters used to write the third data to the one or more second destination data blocks, wherein the transfer of the third data is based at least in part on determining that a second quantity of unavailable source data blocks of the first portion of the memory system satisfies a second threshold, and wherein the second quantity of unavailable source data blocks is based at least in part on writing the second data (Shen: [0017]: “Data to be written to the data storage device, sent from a host controller, is written to the first data storage area media partition until such partition is full or nearly full, and then transferred to the second data storage area media partition. LBAs for the first data storage area media partition are remapped to the physical block addresses of the data transferred to the second data storage area media partition, and a new set of LBAs is mapped to the first data storage area media partition for future write commands from the host controller”) < Examiner note: without further details in claim, the first set of parameters and the second set of parameter are interpreted as the same which is the second write speed taught by Shen. Also, the first threshold and the second threshold are interpreted having the same value which is the threshold level of storage taught by Shen> .
Regarding claims 10 and 19, these claims limitations are significantly similar to those of claim 1, and, therefore, are rejected on the same grounds.
Regarding claim 4, Shen further teaches The apparatus of claim 1, wherein the first set of parameters is associated with a first duration associated with writing each bit of the first data and the second set of parameters is associated with a second duration associated with writing each bit of the third data, wherein the second duration is less than the first duration (Shen: [0030]: “Although the first media partition 110 has been described as an unshingled media partition, and the second media partition 112 has been described as a shingled media partition, it should be understood that the embodiments of the present disclosure may be applied to any system in which one portion of a storage device has a slower write speed than a second portion of the storage device”).
Regarding claim 13, these claims limitations are significantly similar to those of claim 4, and, therefore, are rejected on the same grounds.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shen (2020/0356295) hereinafter Shen as applied to claims 1, 10 and 19 respectively above, and further in view of Burka et al (2012/0239709) hereinafter Burka.
Regarding claim 2, Shen does not teach the current limitations of claim 2.
However, Burka teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: store one or more bits indicating that the third data was transferred to the one or more second destination data blocks of the memory system according to the second set of parameters used to write the third data to the one or more second destination data blocks (Burka: [0043]: “When an object is moved to a destination cache 402, its mark bit is set in the corresponding mark map cache”).
Disclosures by Shen and Burka are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include setting a mark bit after moving data to the destination area taught by Burka. The motivation for setting a mark bit after moving data to the destination area by paragraph [0043] of Burka is for indicating successfully copying objects to the destination.
Regarding claims 11 and 20, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shen (2020/0356295) hereinafter Shen in view of Burka et al (2012/0239709) hereinafter Burka as applied to claims 2 and 10 respectively above, and further in view of Lin (2018/0181454) hereinafter Lin.
Regarding claim 3, Shen and Burka do not teach the current limitations of claim 3.
However, Lin teaches The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: perform, based at least in part on determining that a duration following a last access activity from a host system coupled with the memory system has satisfied a threshold duration, a refresh operation of one or more data blocks of the memory system based at least in part on determining that the one or more data blocks are prioritized for the refresh operation, wherein determining that the one or more data blocks are prioritized for the refresh operation is based at least in part on reading the one or more bits indicating that the third data was transferred to the one or more second destination data blocks according to the second set of parameters, wherein the one or more data blocks comprises the one or more second destination data blocks (Lin: [0042]: “a data refresh can be triggered before data becomes unreliable, e.g., when the data's age exceeds a data retention time threshold. A data retention time threshold can be defined based on a device's endurance and data retention (EDR) characterization result for a specific temperature, usually the average application temperature. The data age of each data in the device may be recorded as a data write-in time table by a timer. Periodically, the table can be checked to refresh the data when the data age meets the data retention time threshold”).
Disclosures by Shen, Burka and Lin are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen/Burka to include refreshing memory block based on age condition taught by Lin. The motivation for include refreshing memory block based on age condition by paragraph [0042] of Lin is for avoiding data retention errors.
Regarding claim 12, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Claims 5-7 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Shen (2020/0356295) hereinafter Shen as applied to claims 1 and 10 respectively above, and further in view of Yuan et al (2020/0387328) hereinafter Yuan.
Regarding claim 5, Shen does not teach the current limitations of claim 5.
However, Yuan teaches The apparatus of claim 1, wherein: determining that the first quantity of unavailable source data blocks of the first portion of the memory system satisfies the first threshold comprises determining that a first quantity of valid source data blocks of the first portion of the memory system satisfies a first threshold quantity of valid source data blocks, wherein the first quantity of unavailable source data blocks comprises the first quantity of valid source data blocks and the first threshold comprises the first threshold quantity of valid source data blocks (Yuan: Fig. 2: threshold 210; [0028]: “When the amount of used storage space in the first storage device 120 is higher than the threshold 210, then the first storage device 120 is in migration state, i.e. at this point the first storage device 120 moves data to the second storage device 130”),
and determining that the second quantity of unavailable source data blocks of the first portion of the memory system satisfies the second threshold comprises determining that a second quantity of valid source data blocks of the first portion of the memory system satisfies a second threshold quantity of valid source data blocks, wherein the second quantity of unavailable source data blocks comprises the second quantity of valid source data blocks and the second threshold comprises the second threshold quantity of valid source data blocks (Yuan: Fig. 2: threshold 210; [0028]: “When the amount of used storage space in the first storage device 120 is higher than the threshold 210, then the first storage device 120 is in migration state, i.e. at this point the first storage device 120 moves data to the second storage device 130”; [0029]: “It will be understood the threshold 210 is not fixed but variable during operation of the storage system”).
Disclosures by Shen and Yuan are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include migrating data when the amount of used storage space is higher than the variable available space threshold taught by Yuan. The motivation for include migrating data when the amount of used storage space is higher than the variable available space threshold by paragraph [0029] of Yuan is for improving available space based on a write velocity from an outside device.
Regarding claim 14, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Regarding claim 6, Shen does not teach the current limitations of claim 6.
However, Yuan further teaches The apparatus of claim 1, wherein: determining that the first quantity of unavailable source data blocks of the first portion of the memory system satisfies the first threshold is based at least in part on determining that a first quantity of available addresses of a logical address space satisfies a first threshold quantity of addresses (Yuan: Fig. 2: threshold 210; [0028]: “When the amount of used storage space in the first storage device 120 is higher than the threshold 210, then the first storage device 120 is in migration state, i.e. at this point the first storage device 120 moves data to the second storage device 130”),
and determining that the second quantity of unavailable source data blocks of the first portion of the memory system satisfies the second threshold is based at least in part on determining that a second quantity of available addresses of the logical address space satisfies a second threshold quantity of addresses (Yuan: Fig. 2: threshold 210; [0028]: “When the amount of used storage space in the first storage device 120 is higher than the threshold 210, then the first storage device 120 is in migration state, i.e. at this point the first storage device 120 moves data to the second storage device 130”; [0029]: “It will be understood the threshold 210 is not fixed but variable during operation of the storage system”).
Disclosures by Shen and Yuan are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include migrating data when the amount of used storage space is higher than the variable available space threshold taught by Yuan. The motivation for include migrating data when the amount of used storage space is higher than the variable available space threshold by paragraph [0029] of Yuan is for improving available space based on a write velocity from an outside device.
Regarding claim 15, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Regarding claim 7, Shen does not teach the current limitations of claim 7.
However, Yuan further teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: transfer, after the transfer of the third data, fourth data from one or more fourth source data blocks of the first portion of the memory system to one or more third destination data blocks of the second portion of the memory system according to the first set of parameters based at least in part on determining that a third quantity of unavailable source data blocks of the first portion of the memory system satisfies the first threshold and fails to satisfy the second threshold (Yuan: [0036]: “A minimum value 410 and a maximum value 420 may be set for the threshold 210. Here the minimum value 410 and the maximum value 420 are determined based on the storage volume of the first storage device 120. For example, the minimum value 410 and the maximum value 420 may be set according to a specific percentage of the storage volume or a specific value. The minimum value 410 may be set to 40% of the storage volume or other value, and the maximum value 420 may be set to 80% of the storage volume or other value. According to example implementations of the present disclosure, the threshold 210 may be selected between the minimum value 410 and the maximum value 420”) .
Disclosures by Shen and Yuan are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include migrating data when the amount of used storage space is higher than the variable available space threshold taught by Yuan. The motivation for include migrating data when the amount of used storage space is higher than the variable available space threshold by paragraph [0029] of Yuan is for improving available space based on a write velocity from an outside device.
Regarding claim 16, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Claims 8, 9, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shen (2020/0356295) hereinafter Shen as applied to claims 1 and 10 respectively above, and further in view of Lin (2018/0181454) hereinafter Lin.
Regarding claim 8, Shen does not teach the current limitations of claim 8.
However, Lin teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: write the first data to the one or more first source data blocks of the first portion of the memory system, wherein writing the first data and the second data comprises programming the first data and the second data to the one or more first source data blocks and the one or more second source data blocks using a single bit, a dual bit, or a triple bit programming operation (Lin: [0034]: “Flash memory controller 114 receives requests from host memory controller 106 for access to memory devices 116 to write data to memory devices 116 or read data from memory devices 116”; [0036]: “Examples of memory devices 116 may include……single-level cell (SLC) devices, triple-level cell (TLC) devices, multi-level cell (MLC) devices, or combinations thereof”).
Disclosures by Shen and Lin are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include memory system using single level cell blocks taught by Lin. The motivation for include memory system using single level cell blocks by paragraph [0063] of Lin is because of the greater data reliability of the SLC block.
Regarding claim 17, these claims limitations are significantly similar to those of claim 8, and, therefore, are rejected on the same grounds.
Regarding claim 9, Shen does not teach the current limitations of claim 9.
However, Kane further teaches The apparatus of claim 8, wherein transferring the first data to the one or more first destination data blocks and the third data to the one or more second destination data blocks is configured to cause the apparatus to: program the first data to the one or more first destination data blocks and the third data to the one or more second destination data blocks using a quad-level programming operation (Kane: [0037]: “In addition to performing transfer operations from lower density blocks to higher density blocks (e.g., migration operations)”; [0034]: “Examples of multiple-level cells include bi-level cells (BLCs) which may be configured to each store two bits of information, tri-level cells (TLCs) which may be configured to each store three bits of information, and quad-level cells (QLCs) which may be configured to each store four bits of information”).
Disclosures by Shen and Kane are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate transferring data from a first partition to second partition of a storage device when a threshold level of storage in the first media partition is reached taught by Shen to include memory system including lower density blocks and higher density blocks taught by Kane. The motivation for include memory system including lower density blocks and higher density blocks by paragraph [0037] of Kane is for performing various types of transfer operations.
Regarding claim 18, these claims limitations are significantly similar to those of claim 9, and, therefore, are rejected on the same grounds.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. These references include:
Kao (2021/0064240), which teaches the method of data moving between a first data storage unit and a second data storage unit. The first data storage unit is accessed by a host-side control unit with high-sped channer, and data moving between the first storage unit and the second storage unit uses the low-speed channel. The method discloses monitoring the storable space of the first data storage unit is lower than a predetermined threshold, the storage controller of the first data storage unit moves partial data in the first storage unit stored in the first data storage unit to the second data storage unit; and
Seok (2024/0118809), which teaches a memory system that migrating data from SLC to MLC. The memory system stores data entries in the memory device by using SLC buffer during a write operation to improve write speed. After that, the memory system 110 may move or migrate the data entries stored in the SLC buffer to either the HPB region 162 or the FBO region 164 to improve read speed. The HPB area 162 and the FBO area 164 may include multi-level cell (MLC) memory blocks in a case of a size of a file or the group of data entries is larger than, or equal to the preset standard, the memory system 110 can migrate the data entries to the FBO region.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAN V DOAN whose telephone number is (571)270-7250. The examiner can normally be reached Monday, Wednesday and Thursday from 10:45 AM to 4:45PM EST.
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/HAN V DOAN/Examiner, Art Unit 2137 /Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137