DETAILED ACTION
This Office action is in response to the preliminary amendment filed on 20 May 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shirakawa et al. (US Patent 6,525,950; hereinafter “Shirakawa”).
In re claim 1, Shirakawa discloses a semiconductor module (Figs. 1-3) comprising:
a plurality of semiconductor chips (Fig. 2: 13a-f; Fig. 3: 18a-f);
a first power source terminal (3a or 3b);
a second power source terminal (2a or 2b);
a first intermediate point terminal (4) and a second intermediate point terminal (5) thus forming a bridge circuit in the semiconductor module (see bridge circuit Figs. 3 and 9), wherein
the first power source terminal and the second power source terminal are disposed adjacently to each other (Figs. 1 and 2: terminal 3a is adjacent to terminal 2a; terminal 3b is adjacent to terminal 2b),
the first intermediate point terminal and the second intermediate point terminal are disposed adjacently to each other (Figs. 1 and 2: terminal 4 is adjacent to terminal 5), and
at a time using the semiconductor module, currents flow in opposite directions with respect to the first power source terminal and the second power source terminal (col. 6: 5-19), and currents flow in opposite directions with respect to the first intermediate point terminal and the second intermediate point terminal (see col. 2 line 62 – col. 3 line 9 and Fig. 8: when used to power the induction motor load 35 as shown, it is the understood operation that at a given time, the positive electrical current output through one of the output terminals 4, 5, 6 flows through the motor windings and is returned as negative electrical current through another of the output terminals 4, 5, 6; that is, electrical current flows in opposite directions through a given pair of the terminals 4, 5, 6 at any given time during operation of the bridge circuit and motor), and
an outer lead portion of the first power source terminal and an outer lead portion of the second power source terminal are disposed on one side of the semiconductor module (Fig. 2: outer lead portions of terminals 3a, 2a or terminals 3b, 2b are disposed on the upper/top side of the semiconductor module), and an outer lead portion of the first intermediate point terminal and an outer lead portion of the second intermediate point terminal are disposed on an other side of the semiconductor module opposite to the one side of the semiconductor module (Fig. 2: outer lead portions of terminals 4, 5 are disposed on the lower/bottom side of the semiconductor module).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the closest prior art in Shirakawa discloses the invention according to claim 1 as explained above, and further discloses first to fourth wiring patterns (Fig. 2: see various wiring portions formed by bus bars 9, 10, substrates 12a-f and bond wires 14a-l), wherein
the plurality of semiconductor chips are first to fourth semiconductor chips (e.g., Fig. 2: 13a-d; Figs. 4, 9: 18a-d) each having a first electrode and a second electrode (e.g., source and drain electrodes),
the bridge circuit is configured such that the first semiconductor chip and the third semiconductor chip form a high side (Fig. 9: 18a and 18c form high-side switches), and the second semiconductor chip and the fourth semiconductor chip form a low side (Fig. 9: 18b and 18d form low-side switches),
the first power source terminal is connected to the first wiring pattern (Fig. 2: power source terminal 3a or 3b connect, e.g., to bus bar 10), and assuming one side out of a plurality of sides of the first wiring pattern as a first side, within a predetermined range of the first side, a recessed portion having a recessed shape as viewed in a plan view of the first wiring pattern is formed (Fig. 2: the portion of bus bar 10 that is orthogonal to the plan of the underlying module substrate 17 is considered a recessed portion in plan view), and, the second power source terminal is connected to the second wiring pattern (Fig. 2: power source terminal 2a or 2b connect to bus bar 9) and,
the third wiring pattern (Fig. 2: e.g., bond wires 14c and/or substrate 12a) is disposed adjacently to the first wiring pattern and the second wiring pattern (see Fig. 2), the second semiconductor chip is mounted on the third wiring pattern (Fig. 2: semiconductor chip 13b mounted on substrate 12a), and the first intermediate point terminal is connected to the third wiring pattern (in this case, output terminal 6 may be considered as one of the intermediate point terminals equivalently to other intermediate terminals 4, 5),
the fourth wiring pattern (Fig. 2: 12c) is disposed adjacently to the first wiring pattern and the second wiring pattern (see Fig. 2), the fourth semiconductor chip is mounted on the fourth wiring pattern (Fig. 2: semiconductor chip 13d mounted on substrate 12c), and the second intermediate point terminal is connected to the fourth wiring pattern (Fig. 2: intermediate point terminal 5 connected to substrate 12c),
a first electrode of the first semiconductor chip is connected to the third wiring pattern via the first connection member (Fig. 2: first chip 13a connected to third wiring pattern 12a by bond wires 14b),
a second electrode of the first semiconductor chip is connected to the first wiring pattern (Fig. 2: 13a connected to bus bar 10 by bond wires 14a),
a first electrode of the second semiconductor chip is connected to the second wiring pattern via a second connecting member (Fig. 2: chip 13b connected to bus bar 9 through bond wires 14c),
a second electrode of the second semiconductor chip is connected to a third wiring pattern (Fig. 2: chip 13b connected to substrate 12a),
a first electrode of the third semiconductor chip is connected to the fourth wiring pattern via a third connection member (Fig. 2: chip 13c connected to substrate 12c by bond wires 14f),
a second electrode of the third semiconductor chip is connected to the first wiring pattern (Fig. 2: chip 13c connected to bus bar 10 by bond wires 14e),
a first electrode of the fourth semiconductor chip is connected to the second wiring pattern via a fourth connection member (Fig. 2: chip 13d connects to bus bar 9 by bond wires 14g), and
a second electrode of the fourth semiconductor chip is connected to the fourth wiring pattern (Fig. 2: chip 13d connected to substrate 12c).
However, Shirakawa does not disclose that the first semiconductor chip and the third semiconductor chip are mounted at positions that sandwich the recessed portion of the first wiring pattern; and as viewed in a plan view, three sides of the second wiring pattern are surrounded by the recessed portion of the first wiring pattern. Rather in Shirakawa’s Fig. 2, the semiconductor chips are all disposed on the plane of the underlying module substrate 17 and do not sandwich the recessed (i.e., vertical) portion of bus bar 10 as the first wiring portion. Further, the bus bar 9 as the second wiring portion is not surrounded on three sides by the recessed (i.e., vertical) portion of the bus bar 10 as the first wiring portion.
Furthermore, the additional prior art on record likewise does not disclose these features, particularly in a manner that would have suggested any obvious modification to the module of Shirakawa that could have resulted in the solution recited in claim 2.
Claims 3-6 each depend, either directly or indirectly, from claim 2 and would therefore be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2014/0159054 discloses a POWER MODULE SEMICONDUCTOR DEVICE having pairs of power terminals disposed on opposite sides of the module.
US 2019/0035771 discloses a POWER MODULE housing a bridge circuit with pairs of power terminals adjacent to one another on opposite sides of the module.
US 2020/0091140 discloses a SEMICONDUCTOR UNIT, SEMICONDUCTOR MODULE, AND SEMICONDUCTOR DEVICE housing a bridge circuit and having terminals disposed adjacent to one another on opposite sides of the module.
US Patent 11,955,451 discloses a Semiconductor Module having pairs of power terminals disposed on opposite sides of the module.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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