Terminal Disclaimer
The terminal disclaimer filed on 10-17-25 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of the full statutory term of the prior patent has been reviewed and is accepted. The terminal disclaimer has been recorded.
DETAILED ACTION
The office action is in response to application filed on 10-13-25. Claims 1-26 are pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-26 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2006/0125452 to Hsieh et al. (“Hsieh”).
Regarding claim 1, Hsieh disclose a system of providing power to a chip on a mainboard (fig. 1), comprising: a first power supply (11), located on the mainboard, wherein the first power supply is configured to receive a first voltage and to provide a second voltage (para; 0020, digital logics may be driven by the voltage level of3.3 volts or 2.5 volts. Accordingly, the mainboard must configure two power rails, including, for example, a 3.3-Volt power rail and a 2.5-Volt power rail. The power rails connect to the south bridge chip for providing the voltages of different voltage levels, which allow the south chip operating normally); a second power supply (13) and a third power supply, wherein the second power supply and the third power supply are located on the mainboard and disposed at different sides of the chip, each of the second power supply and the third power supply is electrically connected to the first power supply to receive the second voltage, the second power supply provides a third voltage to the chip (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics), the third power supply provides a fourth voltage to the chip (fig. 2, different voltage at t0-t3 ); and at least one power supply controller, located on the mainboard, and configured to control operation of the second power supply and the third power supply (para; 0002, chip having a plurality of input power sources, and a power control device thereof).
Regarding claim 2, Hsieh disclose each of the second power supply and the third power supply corresponds to a power supply controller (103) of the at least one power supply controller, and power supply controllers of the second power supply and the third power supply communicate with each other, so as to control the operation of the second power supply and the third power supply respectively (para; 0023, The control unit 103 electrically connects to the comparison unit 101 for receiving the first comparing signal (OUT l) and the second comparing signal (OUT2), and then generates a control signal based on the first and second comparing signals. In the present embodiment, the control unit 103 is a NAND gate, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 3, Hsieh disclose each of the second power supply and the third power supply corresponds to a power supply controller (103) of the at least one power supply controller, the power supply controller of the second power supply is configured to independently control the operation of the second power supply power control device 10 includes a comparison unit 101, a control unit 103, a switch unit 105 and a reference power source 107. The comparison unit 101 electrically connects to the first power rail 11 for receiving the first voltage level and the second power rail 13 for receiving the second voltage level, respectively, the power supply controller of the third power supply is configured to independently control the operation of the third power supply, and power supply controllers of the second power supply and the third power supply do not communicate with each other (para; 0023, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 4, Hsieh disclose a dynamic response speed of the second power supply is greater than a dynamic response speed of the third power supply; and output power of the second power supply in response to a load dynamic change of the chip is greater than output power of the third power supply in response to the load dynamic change of the chip (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 5, Hsieh disclose output impedance of the second power supply is smaller than output impedance of the third power supply; and a dynamic current provided by the second power supply is greater than a dynamic current provided by the third power supply (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 6, Hsieh disclose a system of providing power to a chip on a mainboard (figs. 1-2, 1), comprising: a first power module (11), located on the mainboard, wherein the first power module is configured to receive a first voltage and to provide a second voltage (para; 0020, digital logics may be driven by the voltage level of 3.3 volts or 2.5 volts. Accordingly, the mainboard must configure two power rails, including, for example, a 3.3-Volt power rail and a 2.5-Volt power rail. The power rails connect to the south bridge chip for providing the voltages of different voltage levels, which allow the south chip operating normally); a second power module (13) and a third power module (para; 0002, chip having a plurality of input power sources, and a power control device thereof), wherein the second power module and the third power module are located on the mainboard and disposed at different sides of the chip, each of the second power module and the third power module is electrically connected to the first power module to receive the second voltage, the second power module provides a third voltage to the chip (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics), the third power module provides a fourth voltage to the chip (fig. 2, different voltage at t0-t3 ); and at least one power module controller, located on the mainboard, and configured to control operation of the second power module and the third power module (para; 0002, chip having a plurality of input power sources, and a power control device thereof).
Regarding claim 7, Hsieh disclose each of the second power module and the third power module corresponds to a power module controller of the at least one power module controller, and power module controllers of the second power module and the third power module communicate with each other (para; 0023, The control unit 103 electrically connects to the comparison unit 101 for receiving the first comparing signal (OUT l) and the second comparing signal (OUT2), and then generates a control signal based on the first and second comparing signals. In the present embodiment, the control unit 103 is a NAND gate, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively), so as to control the operation of the second power module and the third power module respectively (para; 0002, chip having a plurality of input power sources, and a power control device thereof).
Regarding claim 8, Hsieh disclose each of the second power module and the third power module corresponds to a power module controller of the at least one power module controller (para; 0002, chip having a plurality of input power sources, and a power control device thereof), the power module controller of the second power module is configured to independently control the operation of the second power module, the power module controller of the third power module is configured to independently control the operation of the third power module (para; 0021, power control device 10 includes a comparison unit 101, a control unit 103, a switch unit 105 and a reference power source 107. The comparison unit 101 electrically connects to the first power rail 11 for receiving the first voltage level and the second power rail 13 for receiving the second voltage level, respectively), and power module controllers of the second power module and the third power module do not communicate with each other (para; 0023, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 9, Hsieh disclose each of the second power module and the third power module corresponds to a power module controller (103) of the at least one power module controller, the power module controller of the second power module is within the second power module (para; 0002, chip having a plurality of input power sources, and a power control device thereof), and the power module controller of the third power module is within the third power module.
Regarding claim 10, Hsieh disclose a dynamic response speed of each of the second power module and the third power module is greater than a dynamic response speed of the first power module (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 11, Hsieh disclose a dynamic response speed of the second power module is greater than a dynamic response speed of the third power module; and output power of the second power module in response to a load dynamic change of the chip is greater than output power of the third power module in response to the load dynamic change of the chip (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 12, Hsieh disclose output impedance of the second power module is smaller than output impedance of the third power module; and a dynamic current provided by the second power module is greater than a dynamic current provided by the third power module (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 13, Hsieh disclose the chip is a multicore chip, comprising a first core and a second core; and the second power module provides the third voltage to the first core, and the third power module provides the fourth voltage to the second core (para; 0005, chips are installed on a circuit board, such as a printed circuit board. To achieve the objectives of increasing the integration of chips, decreasing the power consumption, and enhancing the operation speed, the core circuits of the chips usually have the lower bias voltage and electrical signals with the lower voltage level. However, the chips also include some other circuits, such as the I/O buffer, which need higher voltage levels).
Regarding claim 14, Hsieh disclose a system of providing power to a chip on a mainboard (figs. 1-2), comprising: a first power module (11) and a second power module (13), wherein the first power module and the second power module are located on the mainboard, each of the first power module and the second power module is configured to receive a first voltage, the first power module provides a second voltage, and the second power module provides a third voltage ((para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics) and fig. 2, different voltage at t0-t3 ); a third power module and a fourth power module, wherein the third power module and the fourth power module are located on the mainboard, the third power module is electrically connected to the first power module to receive the second voltage, the fourth power module is electrically connected to the second power module to receive the third voltage, the third power module and the first power module are disposed at a first side of the chip, the fourth power module and the second power module are disposed at a second side of the chip, the third power module provides a fourth voltage to the chip, the fourth power module provides a fifth voltage to the chip (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics); and at least one power module controller (103), located on the mainboard, and configured to control operation of the third power module and the fourth power module.
Regarding claim 15, Hsieh disclose each of the third power module and the fourth power module corresponds to a power module controller of the at least one power module controller, and power module controllers of the third power module and the fourth power module communicate with each other, so as to control the operation of the third power module and the fourth power module respectively (para; 0023, The control unit 103 electrically connects to the comparison unit 101 for receiving the first comparing signal (OUT l) and the second comparing signal (OUT2), and then generates a control signal based on the first and second comparing signals. In the present embodiment, the control unit 103 is a NAND gate, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 16, Hsieh disclose each of the third power module and the fourth power module corresponds to a power module controller of the at least one power module controller, the power module controller of the third power module is configured to independently control the operation of the third power module, the power module controller of the fourth power module is configured to independently control the operation of the fourth power module, and power module controllers of the third power module and the fourth power module do not communicate with each other (para; 0023, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 17, Hsieh disclose each of the third power module and the fourth power module corresponds to a power module controller of the at least one power module controller, the power module controller of the third power module is within the third power module, and the power module controller of the fourth power module is within the fourth power module (para; 0023, The control unit 103 electrically connects to the comparison unit 101 for receiving the first comparing signal (OUT l) and the second comparing signal (OUT2), and then generates a control signal based on the first and second comparing signals. In the present embodiment, the control unit 103 is a NAND gate, which has two inputs connecting to the output OUT l of the first comparator 1011 and the output OUT2 of the second comparator 1012 respectively).
Regarding claim 18, Hsieh disclose a dynamic response speed of the third power module is greater than a dynamic response speed of the first power module; and a dynamic response speed of the fourth power module is greater than a dynamic response speed of the second power module (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 19, Hsieh disclose a dynamic response speed of the third power module is greater than a dynamic response speed of the fourth power module; and output power of the third power module in response to a load dynamic change of the chip is greater than output power of the fourth power module in response to the load dynamic change of the chip (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 20, Hsieh disclose output impedance of the third power module is smaller than output impedance of the fourth power module; and a dynamic current provided by the third power module is greater than a dynamic current provided by the fourth power module (para; 0020, The first and second voltage levels are supplied for the operations of the chip 15. In general, the first power rail 11 and the second power rail 13 of the mainboard 1 have different time delays to reach the regulating voltage states (3.3 volts and 2.5 volts). That is, there is a different between the time delays that the two power rails reach the regulating voltage states).
Regarding claim 21, Hsieh disclose the chip is a multicore chip, comprising at least a first core and a second core (para; 0005, chips are installed on a circuit board, such as a printed circuit board. To achieve the objectives of increasing the integration of chips, decreasing the power consumption, and enhancing the operation speed, the core circuits of the chips usually have the lower bias voltage and electrical signals with the lower voltage level. However, the chips also include some other circuits, such as the I/O buffer, which need higher voltage levels); and the third power module provides the fourth voltage to the first core, and the fourth power module provides the fifth voltage to the second core (para; 0005, chips are installed on a circuit board, such as a printed circuit board. To achieve the objectives of increasing the integration of chips, decreasing the power consumption, and enhancing the operation speed, the core circuits of the chips usually have the lower bias voltage and electrical signals with the lower voltage level. However, the chips also include some other circuits, such as the I/O buffer, which need higher voltage levels).
Regarding claim 22, Hsieh disclose a system of providing power to a chip on a mainboard (fig. 1, mainboard 1), comprising: a first power module (11), wherein the first power module is configured to receive a first voltage and to provide a second voltage; and a second power module (13) and a third power module, wherein each of the second power module and the third power module is electrically connected to the first power module to receive the second voltage, the second power module provides a third voltage to the chip (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics), and the third power module provides a fourth voltage (para; 0002, chip having a plurality of input power sources, and a power control device thereof) to the chip (fig. 2, different voltage at t0-t3 ), wherein the first power module and the second power module are located on a first surface of the mainboard, the third power module is located on a second surface of the mainboard (para; 0019, the chips are installed on a circuit board, such as a printed circuit board), and the first surface and the second surface are opposite to each other.
Regarding claim 23, Hsieh disclose projections of the second power module and the third power module on the mainboard are at least partly overlapped (para; 0019, The chip 15, such as a south bridge chip or a north bridge chip, is a semiconductor chip disposed on the mainboard 1).
Regarding claim 24, Hsieh disclose projections of the first power module and the third power module on the mainboard are at least partly overlapped (para; 0019, The chip 15, such as a south bridge chip or a north bridge chip, is a semiconductor chip disposed on the mainboard 1).
Regarding claim 25, Hsieh disclose a system of providing power to a chip on a mainboard, comprising: a first power module and a second power module, wherein each of the first power module and the second power module is configured to receive a first voltage, the first power module provides a second voltage, and the second power module provides a third voltage (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics); and a third power module and a fourth power module , wherein the third power module is electrically connected to the first power module to receive the second voltage, the fourth power module is electrically connected to the second power module to receive the third voltage, the third power module provides a fourth voltage to the chip, the fourth power module provides a fifth voltage to the chip (para; 0019, the chip 15 can have different voltage levels according to the required bias corresponding to the digital logics); wherein the first power module and the second power module are located on a first surface of the mainboard, the third power module and the fourth power module are located on a second surface of the mainboard (para; 0019, the chips are installed on a circuit board, such as a printed circuit board), and the first surface and the second surface are opposite to each other (fig. 1).
Regarding claim 26, Hsieh disclose projections of the first power module and the third power module on the mainboard are at least partly overlapped (para; 0019, The chip 15, such as a south bridge chip or a north bridge chip, is a semiconductor chip disposed on the mainboard 1), and projections of the second power module and the fourth power module on the mainboard are at least partly overlapped (para; 0019, The chip 15, such as a south bridge chip or a north bridge chip, is a semiconductor chip disposed on the mainboard 1).
Response to argument
Applicant’s argument filed on 10-13-25 with respect to claims 1-26 has been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAYAS G YESHAW whose telephone number is (571)270-1959. The examiner can normally be reached Mon-Sat 9AM-7PM.
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/ESAYAS G YESHAW/Examiner, Art Unit 2836
/DANIEL CAVALLARI/Primary Examiner, Art Unit 2836