Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-8 and 13-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dung(Designing SPI to I2C protocol converter base on ASIC Tech), cited by Applicant.
Regarding claim 1, Dung discloses a system for converting serial data, the system comprising: a first input connected to a chip select signal(Figure 1, SS); a second input connected to an input clock signal(Figure 1, SCLK); a third input connected to an input data signal(Figure 1, MOSI); a first output to provide an output clock signal(Figure 1, SCL); a second output to provide an output data signal(Figure 1, SDA); and a logic circuit operative to sequentially perform the following steps: detect the chip select signal transitioning to a logical zero state(Section 2.2, During communication, the master can only pick a slave-based device by dragging the device’s SS signal pin to a low level), initialize the output clock signal and the output data signal, mirror the input clock signal to the output clock signal as the input clock signal is received at the second input, transfer the input data signal to the output data signal as the input data signal is received at the third input(Section 2.5.1, Figure 5-6, When the SPI master pulls the SS_N signal pin to a low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C interface standard as the start bit, the address bits, the ACK bit and the stop bit. The data after being filtered by the SPI slave block continues to be processed by the processor bloc and sent to the I2C master block for transmission to the I2C slave devices), detect the chip select signal transition to a logical one state(Figure 5, SS_n transition to logic one), and reset the output clock signal and the output data signal(Figure 6, Stop condition of transitioning to default logic one).
Regarding claim 2, Dung discloses system of claim 1, wherein the logic circuit comprises a delay element connected in series with the chip select signal and wherein the delay element is operative to output a delayed chip select signal(Figure 4, SPI to I2C bridge control is considered as a delay element).
Regarding claim 6, Dung discloses system of claim 1, further comprising a fourth input, wherein the second output is bidirectional and the logic circuit is further operative to transmit data from the second output to the fourth input(Figure 1, Data read from SDA connected to MISO).
Regarding claim 7, Dung discloses system of claim 1, wherein: the first input, the second input, and the third input are configured to receive signals from a Serial Peripheral Interface protocol, the first output and the second output are configured to provide signals to an Inter-Integrated Circuit protocol(Figure 1, .SPI to I2C).
Regarding claim 8, Dung discloses system of claim 1 further comprising a programmable logic device including the first input, the second input, the third input, the first output, the second output, and the logic circuit(Section 4.1, FPGA).
Regarding claim 13, Dung discloses method for converting serial data, comprising the steps of: detecting a chip select signal transitioning to a logical zero state(Section 2.2, During communication, the master can only pick a salve-based device by dragging the device’s SS signal pin to a low level); responsive to detecting the chip select signal transitioning to the logical zero state: generating an output data signal at the logical zero state(Figure 6, SDA transitioning to zero for the start condition), and generating an output clock signal at the logical zero state after generating the output data signal(Figure 6, SCL transitions to zero for the start condition after SDA transitions to zero); receiving an input data signal(Figure 1, MOSI input signal) and an input clock signal(Figure 1, SCLK input signal); transmitting the input clock signal to the output clock signal; transmitting one bit of the input data signal to the output data signal with each cycle of the input clock signal(Section 2.5.1, Figure 5-6, When the SPI master pulls the SS_N signal pin to a low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C interface standard as the start bit, the address bits, the ACK bit and the stop bit. The data after being filtered by the SPI slave block continues to be processed by the processor bloc and sent to the I2C master block for transmission to the I2C slave devices); and responsive to completing transmission of the input data signal: setting the clock output signal to a logical one state, and setting the data output signal to the logical one state(Figure 6, Stop condition of transitioning SDA and SCL default logic one of the I2C protocol).
Regarding claim 14, Dung discloses method of claim 13, further comprising the steps of: transmitting the chip select signal to a delay element connected in series with the chip select signal; and generating a delayed chip select signal as a function of the chip select signal and a duration of the delay element(Section 2.5.1, Figure 5-6, When the SPI master pulls the SS_N signal pin to a low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C interface standard as the start bit, the address bits, the ACK bit and the stop bit. The data after being filtered by the SPI slave block continues to be processed by the processor bloc and sent to the I2C master block for transmission to the I2C slave devices).
Regarding claim 15, Dung discloses method of claim 14 further comprising the step of generating the output clock signal as a function of the chip select signal, the delayed chip select signal, and the input clock signal(Section 2.5.1, Figure 5-6, When the SPI master pulls the SS_N signal pin to a low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C interface standard as the start bit, the address bits, the ACK bit and the stop bit. The data after being filtered by the SPI slave block continues to be processed by the processor bloc and sent to the I2C master block for transmission to the I2C slave devices).
Regarding claim 16, Dung discloses method of claim 14 further comprising the step of generating the output data signal as a function of the chip select signal, the delayed chip select signal, and the input data signal(Section 2.5.1, Figure 5-6, When the SPI master pulls the SS_N signal pin to a low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C interface standard as the start bit, the address bits, the ACK bit and the stop bit. The data after being filtered by the SPI slave block continues to be processed by the processor bloc and sent to the I2C master block for transmission to the I2C slave devices).
Regarding claim 17, Dung discloses method of claim 16 further comprising the step of selectively enabling a bidirectional data pin as a function of the output data signal(Figure 1, Data read from SDA connected to MISO).
Regarding claim 18, Dung discloses method of claim 17 further comprising the steps of: enabling the bidirectional data pin for data input from another device; and transmitting the data input to a first device generating the chip select signal(Figure 1, Data read from SDA connected to MISO).
Regarding claim 19, Dung discloses method of claim 13, wherein: the chip select signal, the input data signal, and the input clock signal are received from a master device communicating via a Serial Peripheral Interface protocol, and the output data signal and the output clock signal are transmitted to an additional device communicating via an Inter-Integrated Circuit protocol(Figure 1, SPI to I2C).
Regarding claim 20, Dung discloses method of claim 13 wherein the steps are performed on a programmable logic device(Section 4.1, FPGA).
Allowable Subject Matter
Claim 9-12 are allowed.
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or suggest, either alone or in combination, a logical OR gate receiving the chip select signal, the delayed chip select signal, and the clock signal as inputs and an output of the logical OR gate is the output clock signal, which is included in claims 3 and 9.
Conclusion
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187