DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 5, 8, 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210242370 (Lee et al) in view of US 20220140199 (DiMaria).
Concerning claim 1, Lee discloses a light emitting element comprising (Figs. 5 and 7A-8G): a semiconductor stack structure (120) comprising: an N-type semiconductor layer (122) ([0023]); a P-type semiconductor layer (126) ([0023]); and an active layer (124) disposed between the N-type semiconductor layer and the P-type semiconductor layer ([0024]); an intermediate passivation structure (130) disposed on a side surface of the semiconductor stack structure ([0028]); and an insulating layer (230) disposed on the intermediate passivation structure (Fig. 5), and comprising a metal oxide ([0044]), wherein the intermediate passivation structure comprises a crystal structure comprising nitrogen (N), and a material forming the semiconductor stack structure ([0066]).
Lee does not disclose wherein the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element. However, DiMaria discloses a light emitting element (Fig. 2E) that includes an N-type semiconductor layer (204n), a P-type semiconductor layer (204p) ; and an active layer (206) disposed between the N-type semiconductor layer and the P-type semiconductor layer ([0052], for purposes of examination the examiner is relying on at least one of the semiconductor layers to be AlGaN); an intermediate passivation structure (216) disposed on a side surface of the semiconductor stack structure ([0058] for purposes of examination the examiner is relying on this layer be AlN); and an insulating layer (218) disposed on the intermediate passivation structure ([0059] and [0062]), and comprising a metal oxide ([0059] for purposes of examination the examiner is relying on this layer to be HfO2), wherein the intermediate passivation structure comprises nitrogen (N), and a material forming the semiconductor stack structure ([0066]) with the configuration of the insulating and passivation structure being such that the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element (Fig. 2E). DiMaria discloses that this configuration is capable of mitigating the negative effect of surface recombination on reduced light output ([0005]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the intermediate passivation layer and the insulating layer of Lee in view of DiMaria such the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element in order to achieve the advantages disclosed by DiMaria.
Continuing to claim 4, Lee in view of DiMaria discloses wherein the intermediate passivation structure spaces apart an interior of the semiconductor stack structure from the insulating layer (Lee Fig. 5), and the insulating layer comprises a metal oxide comprising at least one metal selected from a group comprising tantalum (Ta), hafnium (Hf), zirconium (Zr), lanthanum (La), silicon (Si), titanium (Ti), and aluminum (Al) (Lee [0044] and DiMaria [0062]).
Considering claim 5, Lee in view of DiMaria discloses wherein the insulating layer comprises insulating layers comprising two or more materials different from each other (Lee [0044], note that the materials of the insulating layer are disclosed as being SOG and Al2O3 which is what the examiner is relying on for purposes of rejection).
Referring to claim 8, Lee in view of DiMaria discloses wherein a diameter of the light emitting element is about 100 µm or less (Lee [0021] and [0049]).
Regarding claim 9, Lee in view of DiMaria discloses wherein the intermediate passivation structure is an intermediate passivation layer (Lee 130) (Lee [0025], note that structure 130 is formed as a structure that has no conductivity), and a first surface of the intermediate passivation layer contacts the semiconductor stack structure, and a second surface of the intermediate passivation layer contacts the insulating layer (Lee Fig. 5).
Pertaining to claim 11, Lee in view of DiMaria discloses wherein the light emitting element comprises a red light emitting element that emits red light (Lee [0047] and [0051]).
Claim(s) 2, 3, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210242370 (Lee et al) in view of US 20170170360 (Bour et al), as applied to claim 1 above and further in view US 20220140199 (DiMaria).
As to claims 2 and 3, Lee in view of DiMaria discloses forming the semiconductor stack and the intermediate passivation structure (Fig. 5).
Lee in view of DiMaria does not disclose wherein the semiconductor stack structure comprises GaP, and the intermediate passivation structure comprises GaPxN(1-x) or wherein the semiconductor stack structure comprises InₓAlyGa(1-x-y)P, and the intermediate passivation structure comprises AlₓInyGa(1-y)PzN(1-z) . However, Bour discloses light emitting element configurations (Fig. 1) that comprise a passivation layer (602) (Figs. 6A-6F and [0099]-[0101]), sidewall passivation layer (170) (Figs. 17A-17F and [0126]-[0128]), and doping of the sidewalls of the light emitting structure with Nitrogen to create a confinement region (242) (Figs. 24A-24C and [0164]-[0165], note that the confinement regions are formed in the semiconductor stack materials to formed a nitride version of the semiconductor stack materials). Bour discloses the use of GaP and AlInGaP as the materials of the semiconductor stack ([0081]). Bour also discloses the combinations and variations of these configurations ([0176]) and that such configurations reduce surface recombination ([0068]) and create vacancies, causing inter-diffusion at the p-n diode layer sidewalls such that a higher bandgap energy is created at the sidewall surfaces that effectively confines the active layer ([0077]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the semiconductor stack materials of Bour (with the doping of the sidewalls with Nitrogen (N) to form confinement regions) as the semiconductor stack materials of Lee in order to reduce surface recombination and create vacancies such that a higher bandgap energy is created at the sidewall surfaces to effectively confine the active layer.
According to claim 7, Lee in view of DiMaria and Bour discloses wherein in a crystal structure of the intermediate passivation structure comprising the GaP, a displacement of P based on a reference position is determined to be within about 8% compared to a bonding length between Ga and P, and the reference position of the P is a position of the P in the crystal structure of the intermediate passivation structure in case that a separate energy is not supplied to the light emitting element (Lee [0026] and Bour [0081], note that the Bour discloses the use of GaP and Lee discloses that the crystal structure of intermediate passivation structure has a hexagonal structure which is disclosed in the specification [0088] as having these features).
Concerning claim 10, Lee in view of DiMaria and Bour discloses wherein the intermediate passivation structure comprises an intermediate passivation area, and the intermediate passivation arca comprises an arca in which a side surface of the semiconductor stack structure is doped with N (Bour [0164]-[0165]).
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210242370 (Lee et al) in view of US 20170170360 (Bour et al) and US 20220140199 (DiMaria).
Continuing to claim 13, Lee discloses a method of manufacturing a light emitting element, comprising (Figs. 5 and 7A-8G): patterning a semiconductor stack structure (120) on a growth substrate (Fig. 7B); forming an intermediate passivation structure (130) on a side surface of the semiconductor stack structure (Fig. 7C); and forming an insulating layer (230) comprising a metal oxide on the intermediate passivation structure (Fig. 8B and [0044]).
Lee does not disclose wherein the semiconductor stack structure comprises GaP, and the intermediate passivation structure comprises GaPₓN(1-ₓ) or wherein the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element. However, Bour discloses light emitting element configurations (Fig. 1) that comprise a passivation layer (602) (Figs. 6A-6F and [0099]-[0101]), sidewall passivation layer (170) (Figs. 17A-17F and [0126]-[0128], note the material of the passivation layer can be Aluminum oxide), and doping of the sidewalls of the light emitting structure with Nitrogen to create a confinement region (242) (Figs. 24A-24C and [0164]-[0165], note that the confinement regions are formed in the semiconductor stack materials to formed a nitride version of the semiconductor stack materials). Bour discloses the use of GaP and AlInGaP as the materials of the semiconductor stack ([0081]). Bour also discloses the combinations and variations of these configurations ([0176]) and that such configurations reduce surface recombination ([0068]) and create vacancies, causing inter-diffusion at the p-n diode layer sidewalls such that a higher bandgap energy is created at the sidewall surfaces that effectively confines the active layer ([0077]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the semiconductor stack material GaP of Bour (with the doping of the sidewalls with Nitrogen (N) to form confinement regions/passivation layer) as the semiconductor stack material of Lee in order to reduce surface recombination and create vacancies such that a higher bandgap energy is created at the sidewall surfaces to effectively confine the active layer.
Additionally, DiMaria discloses a light emitting element (Fig. 2E) that includes an N-type semiconductor layer (204n), a P-type semiconductor layer (204p) ; and an active layer (206) disposed between the N-type semiconductor layer and the P-type semiconductor layer ([0052], for purposes of examination the examiner is relying on at least one of the semiconductor layers to be AlGaN); an intermediate passivation structure (216) disposed on a side surface of the semiconductor stack structure ([0058] for purposes of examination the examiner is relying on this layer be AlN); and an insulating layer (218) disposed on the intermediate passivation structure ([0059] and [0062]), and comprising a metal oxide ([0059] for purposes of examination the examiner is relying on this layer to be HfO2), wherein the intermediate passivation structure comprises nitrogen (N), and a material forming the semiconductor stack structure ([0066]) with the configuration of the insulating and passivation structure being such that the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element (Fig. 2E). DiMaria discloses that this configuration is capable of mitigating the negative effect of surface recombination on reduced light output ([0005]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the intermediate passivation layer and the insulating layer of Lee in view of DiMaria such the insulating layer does not extend substantially past the intermediate passivation structure in a length direction of light emitting element in order to achieve the advantages disclosed by DiMaria.
Considering claim 14, Lee in view of Bour and DiMaria discloses wherein the forming of the intermediate passivation structure comprises forming an intermediate passivation layer comprising GaPxN(1-x) on the side surface of the semiconductor stack structure (Bour [0164], note that the semiconductor stack material is disclosed as being GaP and that Nitrogen (N) is implanted into the sidewalls to realize the formation of GaPxN(1-x)).
Referring to claim 15, Lee in view of Bour and DiMaria discloses wherein the forming of the intermediate passivation structure comprises doping the side surface of the semiconductor stack structure with nitrogen (N) (Bour [0164], note that the semiconductor stack material is disclosed as being GaP and that Nitrogen (N) is implanted into the sidewalls to realize the formation of GaPxN(1-x)).
Regarding claim 16, Lee in view of Bour and DiMaria discloses wherein the insulating layer comprises a metal oxide comprising at least one metal selected from a group comprising tantalum (Ta), hafnium (Hf), zirconium (Zr), lanthanum (La), silicon (Si), titanium (Ti), and aluminum (Al) (Lee [0044]).
Pertaining to claim 17, Lee in view of Bour and DiMaria discloses further comprising: separating a structure comprising the semiconductor stack structure, the intermediate passivation structure, and the insulating layer (Lee Fig. 8D).
As to claim 18, Lee in view of Bour and DiMaria discloses wherein the patterning of the semiconductor stack structure comprises sequentially growing semiconductor layers on the growth substrate; and etching the grown semiconductor layers (Lee Fig. 7A).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210242370 (Lee et al) in view of US 20220140199 (DiMaria)as applied to claim 1 above, and further in view of US 20200076223 (Kuriki et al).
Considering claim 6, Lee in view of DiMaria discloses forming the metal oxide (aluminum oxide) containing insulating layer and an Indium (In) containing semiconductor stack material (Lee [0023]).
Lee in view of DiMaria does not explicitly disclose wherein the metal oxide forming the insulating layer has a bonding energy greater than a bonding energy of the material forming the semiconductor stack structure. However, Kuriki discloses The element M is an element having high bonding energy with oxygen, for example. The element M , which is disclosed to be aluminum (Al), gallium (Ga), tin (Sn), or the like. boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), is an element having higher bonding energy with oxygen than indium, for example. Such metal oxide crystallizes more easily ([0027]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to choose the metal oxide of the insulating layer of Lee to have a bonding energy greater than a bonding energy of the semiconductor stack material (In) to allow for easier crystallization of the layer as disclosed by Kuriki.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210242370 (Lee et al) in view of US 20220140199 (DiMaria) as applied to claim 1 above, and further in view of US 20230209981 (Gao et al).
Referring to claim 12, Lee in view of DiMaria discloses forming the light emitting element.
Lee in view of DiMaria does not disclose a display device, comprising the light emitting element according to claim 1, that allows the light emitting element to be supplied with an energy of about 0.15 eV or less in case that the light emitting element emits light. However, Gao discloses operating a display device at 0.1 eV (Table 2) and that such supplied energy leads to the light-emitting lifetime of the light-emitting device being longer, the operating voltage reduced, the power consumption reduced, and the light-emitting efficiency of the light-emitting device is further improved ([0063]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to allow the light emitting element to be supplied with the 0.1 eV energy as disclosed by Gao in order to achieve the aforementioned advantages.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240038177 (Kim et al) in view of US 20220246802 (Kim et al, hereafter referred to as Kim’802).
According to claim 19, Kim discloses a display device (Figs. 7 and 8), comprising: a base layer (10); and sub-pixels (RPA, GPA, BPA) disposed on the base layer (Figs. 7 and 8 and [0105]), wherein each of the sub-pixels comprises series parts (RE2, GE2, BE2) comprising light emitting elements (310), an anode connection electrode (311) electrically connected to the series parts, and a cathode connection electrode (313) electrically connected to the series parts (Fig. 8), the sub-pixels comprise a first sub-pixel that provides red light, a second sub-pixel that provides green light, and a third sub-pixel that provides blue light ([0105]), the light emitting elements comprise first light emitting elements comprised in the first sub-pixel, second light emitting elements comprised in the second sub-pixel, and third light emitting elements comprised in the third sub-pixel (Fig. 7), the series parts comprise r red series parts comprised in the first sub-pixel, g green series parts comprised in the second sub-pixel, and b blue series parts comprised in the third sub-pixel, r, g, and b are natural numbers, ([0144], note that it is disclosed that the number of second light emission areas RE2 defined in the second lens area RNE of the red subpixel area RPA may be greater than the number of second light emission areas GE2 defined in the second lens area GNE of the green subpixel area GPA).
Kim does not disclose r is greater than g, r is greater than b, each of the r red series parts comprises a plurality of the first light emitting elements, each of the g green series parts comprises a plurality of the second light emitting elements, and each of the b blue series parts comprises a plurality of the third light emitting elements. However, Kim’802 discloses a light emitting device configuration in which r is greater than g, r is greater than b, each of the r red series parts comprises a plurality of the first light emitting elements, each of the g green series parts comprises a plurality of the second light emitting elements, and each of the b blue series parts comprises a plurality of the third light emitting elements ([0012] and [0195]). Kim’802 also discloses such configuration allows for a display device with improved front surface luminance by disposing different types of light emitting elements that emit colors different from each other in a sub-pixel ([0006]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention of Kim in view of Kim’802 in order to achieve a display device with improved surface luminance.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220173177 (Cho et al) in view of US 20230057334 (Yang).
Referencing claim 20, Cho discloses a display device (Figs. 5A and 6), comprising: a base layer (100); and sub-pixels (Pr, Pg, Pb) disposed on the base layer, and comprising a first sub-pixel comprising a first light emitting element that emits red light (Pr), a second sub-pixel comprising a second light emitting element that emits green light (Pg), and a third sub-pixel comprising a third light emitting element that emits blue light (Pb) ([0128]), wherein the first light emitting element . . . a first size, the second light emitting element . . . has a second size, the third light emitting element . . . a third size, and the first size is greater than the second size or the third size ([0128], note that the size of the red subpixel may be greater than that of the green subpixel).
Cho does not disclose the first light emitting element includes a first active layer having a first size, the second light emitting element includes a second active layer having has a second size, the third light emitting element includes a first active layer having a third size. . . and the second size is greater than the third size. However, Yang discloses a light emitting device configuration that includes a first, second, and third light emitting element with active areas with the first light emitting element includes a first active layer having a first size, the second light emitting element includes a second active layer having has a second size, the third light emitting element includes a first active layer having a third size. . . and the second size is greater than the third size. ([0030] and [0062]), and the first size is greater than the second size or the third size and the second size is greater than the third size (Fig. 10B). Yang discloses that this configuration mitigate color shifts in ambient light reflections ([0062]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the sizes of the light emitting elements in view of Yang such that the first light emitting element includes a first active layer having a first size, the second light emitting element includes a second active layer having has a second size, the third light emitting element includes a first active layer having a third size and the second size is greater than the third size and the first size is greater than the second size or the third size and the second size is greater than the third size in order to mitigate color shift in ambient light reflections.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 13, 19, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 10/01/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
