DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/06/2026 have been fully considered but they are not persuasive.
Regarding claim 1, in response to applicant's argument that Yasuda et al. (US 2021/0135645 A1), hereinafter Yasuda, and Goto et al. (US 2017/0099043 A1), hereinafter Goto, do not disclose the additional circuit, the first filter circuit, third filter circuit, and third IDT configuration, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In this case, the additional circuit configurations of Goto are utilized to achieve the benefit of highly flexible adjustment of attenuation and isolation characteristics of the associated filters (Goto, Para [0062]). Thus, an additional circuit, at least a portion of which is connected in parallel to each of the first filter circuit and the third filter circuit; and of the three or more IDTs, a third IDT is connected to a path connecting the third terminal and the third filter circuit or a path extending through an inside of the third filter circuit each being a portion of the third path is disclosed by Goto (see figure 3A & 9 disclosing the configuration of the additional circuit 400 with first filter 200 and third filter 300), as required by the invention as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, & 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda et al. (US 2021/0135645 A1), hereinafter Yasuda, in view of Goto et al. (US 2017/0099043 A1), hereinafter Goto.
Regarding claim 1, Yasuda discloses, in figure 11A, a multiplexer (Para [0090], “multiplexer 3”) comprising:
three or more filter circuits (10, 20, 40, & 50) with pass bands that are different from one another (Para [0028], [0029], [0091], & [0092], “filter circuit 10…including a pass band that is the first frequency band…filter circuit 20…including a pass band that is a second frequency band…filter circuit 40…including a pass band that is a third frequency band…filter circuit 50…including a pass band that is a fourth frequency band”);
a common terminal (100), a first terminal (110), a second terminal (120), and a third terminal (140);
a first filter circuit in a first path connecting the first terminal and the common terminal (filter 10 connects common terminal 100 and first terminal 110);
a second filter circuit in a second path connecting the second terminal and the common terminal (second filter 20 connected to common terminal 100 and second terminal 120);
a third filter circuit in a third path connecting the third terminal and the common terminal (third filter 40 connected to common terminal 100 and third terminal 140), but fails to disclose an additional circuit, at least a portion of which is connected in parallel to each of the first filter circuit and the third filter circuit; wherein
the additional circuit includes three or more IDTs aligned along a first direction and two reflectors on both outer sides of the three or more IDTs in the first direction;
of the three or more IDTs, a first IDT is connected to a path connecting the first terminal and the first filter circuit or a path extending through an inside of the first filter circuit, each being a portion of the first path;
of the three or more IDTs, a third IDT is connected to a path connecting the third terminal and the third filter circuit or a path extending through an inside of the third filter circuit each being a portion of the third path; and
of the three or more IDTs, a second IDT is connected to a first common terminal side path that is a portion of the first path and connects the first filter circuit and the common terminal, a third common terminal side path that is a portion of the third path and connects the third filter circuit and the common terminal, or a second common terminal side path that is a portion of the second path and connects the second filter circuit and the common terminal.
However, Goto discloses, in figure 3A & 9, an additional circuit (400), at least a portion of which is connected in parallel to each of the first filter circuit and the third filter circuit (portion of circuit 400 is connected in parallel with filter 200 and a portion of circuit 400 is connected in parallel with filter 300); wherein
the additional circuit includes three or more IDTs aligned along a first direction and two reflectors on both outer sides of the three or more IDTs in the first direction (figure 3A discloses additional circuit 400 consisting of IDTs 410, 420, & 430 and reflectors 462 & 464);
of the three or more IDTs (IDTs 410, 420, & 430), a first IDT is connected to a path connecting the first terminal and the first filter circuit or a path extending through an inside of the first filter circuit, each being a portion of the first path (IDT 410 connected to first path connecting first terminal 202 and first filter 200 via capacitor 205);
of the three or more IDTs (IDTs 410, 420, & 430), a third IDT is connected to a path connecting the third terminal and the third filter circuit or a path extending through an inside of the third filter circuit each being a portion of the third path (IDT 430 connected to a third path connecting terminal 203 and third filter 300 via capacitor 206); and
of the three or more IDTs (IDTs 410, 420, & 430), a second IDT is connected to a first common terminal side path that is a portion of the first path and connects the first filter circuit and the common terminal (IDT 420 is connected to first common terminal side path that connects filter 200 and common terminal 201), a third common terminal side path that is a portion of the third path and connects the third filter circuit and the common terminal (IDT 420 is connected to a third common terminal side path that connects filter 300 and the common terminal 201), or a second common terminal side path that is a portion of the second path and connects the second filter circuit and the common terminal.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the additional circuit of Goto in the multiplexer of Yasuda, to achieve the benefit of highly flexible adjustment of attenuation and isolation characteristics of the associated filters of the multiplexers (Goto, Para [0062]).
Regarding claim 2, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Yasuda continues to disclose, in figure 11A, wherein the first common terminal side path, the third common terminal side path, and the second common terminal side path are at a same potential (an equal potential is seen at each common terminal side path between the filters 10, 20, 40, & 50 and the common terminal 100).
Regarding claim 3, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 9, wherein each of the three or more IDTs includes a pair of comb- shaped electrodes (Para [0106], “comb-shaped electrodes of the first to third IDT electrodes 410, 420, & 430”);
the pair of comb-shaped electrodes include one comb-shaped electrode and another comb-shaped electrode (each of the first to third IDT electrodes 410, 420, & 430 constitutes two comb-shaped electrodes with a connection to its associated filter path and a second connection to ground, respectively. See figure 8);
the one comb-shaped electrode of the first IDT is connected to the path connecting the first terminal and the first filter circuit or the path extending through the inside of the first filter circuit (a comb-shaped electrode of the first IDT 410 is connected to the path connecting the first terminal 202 and the first filter 200);
the one comb-shaped electrode of the third IDT is connected to the path connecting the third terminal and the third filter circuit or the path extending through the inside of the third filter circuit (a comb-shaped electrode of the third IDT 430 is connected to the path connecting the terminal 203 and the filter 300);
the one comb-shaped electrode of the second IDT is connected to the first common terminal side path, the third common terminal side path, or the second common terminal side path (a comb-shaped electrode of the second IDT 410 is connected to the common terminal path for the filters 200 & 300); and
each of the another comb-shaped electrodes of the first IDT, the second IDT, and the third IDT is connected to ground (Para [0106], “grounded comb-shaped electrodes of the first to third IDT electrodes 410, 420, & 430”).
Regarding claim 4, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 9, wherein the second IDT is located between the first IDT and the third IDT in the first direction (IDT 420 is located between IDT 410 and IDT 430).
Regarding claim 6, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Yasuda continues to disclose, in figure 11A, wherein each of the first filter circuit (Para [0114], “filter circuit 10 may be a transmitting filter”) and the third filter circuit (40) is a transmission filter circuit (Para [0091], “filter circuit 40 includes a terminal connected to the common terminal 100 and a terminal connected to the input/output termina 140”…[i.e., may be utilized as a transmission filter circuit); and
the second filter circuit is a reception filter circuit (Para [0114], “filter circuit 20 may be a receiving filter”).
Regarding claim 7, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 9, wherein a reactance element is provided in each of a path connecting the first filter circuit and the additional circuit and a path connecting the third filter circuit and the additional circuit (capacitor 205 is provided on the path connected the first filter circuit 200 and the circuit 400 and a capacitor 206 is provided on the path connecting the filter circuit 300 and the circuit 400).
Regarding claim 8, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 9, wherein the three or more IDTs are three IDTs including the first IDT, the second IDT, and the third IDT (IDTs 410, 420, & 430).
Regarding claim 9, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Yasuda continues to disclose, in figure 11A, wherein the first, second, and third filter circuits are each connected to an antenna (Para [0056], “common terminal 100 is connected to an antenna”…filters 10, 20, 40, & 50 are connected to common terminal 100).
Regarding claim 15, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 11, wherein the three or more IDTs are four IDTs including the first IDT, the second IDT, the third IDT, and a fourth IDT (Para [0112], “additional circuit 400 can include five IDT electrodes, i.e., first to fifth IDT electrodes 410, 420, 430, 440, & 450”).
Regarding claim 16, Yasuda in view of Goto disclose the multiplexer according to claim 1, and Goto continues to disclose, in figure 11, wherein the three or more IDTs are five IDTs including the first IDT, the second IDT, the third IDT, a fourth IDT, and a fifth IDT (Para [0112], “additional circuit 400 can include five IDT electrodes, i.e., first to fifth IDT electrodes 410, 420, 430, 440, & 450”).
Claims 5 & 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda in view of Goto as applied to claims 1-4, 6-9, & 15-16 above, and further in view of Mori (US 2020/0083865 A1).
Regarding claim 5, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein an attenuation band outside the pass band of the first filter circuit, an attenuation band outside the pass band of the third filter circuit, and the pass band of the second filter circuit at least partially overlap with one another.
However, Mori discloses, in figure 1A, wherein an attenuation band outside the pass band of the first filter circuit (Para [0129], “filter 21 is a band pass filter that…has Band 40 [i.e., 2300-2400 MHz] and band 1Rx [i.e., 2110-2170 MHz] as stop bands”), an attenuation band outside the pass band of the third filter circuit (Para [0132], “filter 23 is a band pass filter that…has band 40 and band 41 [i.e., 2496-2690 MHz] as stop bands”), and the pass band of the second filter circuit at least partially overlap with one another (Para [0131], “filter 22 is a band pass filter that has band 40 as a pass band”…band 40 is the overlap).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the overlapping bands of Mori in the multiplexer of Yasuda and Goto, to achieve the benefit of implementing a multiplexer with high-selectivity and thus increased isolation between the band-pass filters (Mori, Para [0134]).
Regarding claim 10, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein each of the first, second, and third filter circuits includes a plurality of series arm resonators connected in series with one another, and a plurality of parallel arm resonators provided in a path between a node between adjacent series arm resonators of the plurality of series arm resonators and a reference terminal.
However, Mori discloses, in figure 1A, 1B, & 1C, wherein each of the first (21), second (22), and third filter (23) circuits includes a plurality of series arm resonators connected in series with one another (Para [0135], “filter 22 includes, for example, a ladder circuit made up of one or more series arm resonators…and one or more parallel arm resonators [see figure 1B]”), and a plurality of parallel arm resonators (Para [0137], “filter 23 includes, for example, a ladder circuit that is made up of one or more series arm resonators…and one or more parallel arm resonators”) provided in a path between a node between adjacent series arm resonators of the plurality of series arm resonators and a reference terminal (Para [0138], “as in the case of the filter 22 or the filter 23, the filter 21 is made up of a ladder circuit including series arm resonators and parallel arm resonators”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the ladder circuit of Mori in the filter circuits of Yasuda and Goto, to achieve the benefit of a miniaturized and low-profile multiplexer with sufficient high-selectivity (Mori, Para [0046]).
Regarding claim 11, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein each of the first, second, and third filter circuits is a ladder band pass filter.
However, Mori discloses, in figure 1A, 1B, & 1C, wherein each of the first, second, and third filter circuits is a ladder band pass filter (Para [0138], “as in the case of the filter 22 or the filter 23, the filter 21 is made up of a ladder circuit including series arm resonators and parallel arm resonators”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the ladder circuit of Mori in the filter circuits of Yasuda and Goto, to achieve the benefit of a miniaturized and low-profile multiplexer with sufficient high-selectivity (Mori, Para [0046]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda in view of Goto as applied to claims 1-4, 6-9, & 15-16 above, and further in view of Nosaka (US 2020/0220522 A1).
Regarding claim 12, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein a pass band of the first filter circuit is about 703 MHz to about 748 MHz.
However, Nosaka discloses, in figure 23A, wherein a pass band of the first filter circuit is about 703 MHz to about 748 MHz (Para [0192], “filter device according to the present embodiment is applied as a long term evolution (LTE) band 28 transmission filter [transmission passband: 703 to 748 MHz]”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the pass band of Nosaka in the first filter circuit of Yasuda and Goto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., utilizing a filter of a multiplexer within a desired frequency range for its associated application], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda in view of Goto as applied to claims 1-4, 6-9, & 15-16 above, and further in view of Nosaka (US 2019/0181838 A1).
Regarding claim 13, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein a pass band of the second filter circuit is about 758 MHz to about 821 MHz.
However, Nosaka discloses, in figure 18A, wherein a pass band of the second filter circuit is about 758 MHz to about 821 MHz (Para [0126] & [0268], “B28+20Rx: 758-821 MHz…variable filter 26B is a filter…in which the pass band is set to the reception band of Band 28+20”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the pass band of Nosaka in the second filter circuit of Yasuda and Goto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., utilizing a filter of a multiplexer within a desired frequency range for its associated application], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda in view of Goto as applied to claims 1-4, 6-9, & 15-16 above, and further in view of Mori (US 2021/0242853 A1).
Regarding claim 14, Yasuda in view of Goto disclose the multiplexer according to claim 1, but fails to disclose wherein a pass band of the third filter circuit is about 832 MHz to about 862 MHz.
However, Mori discloses, in figure 1, wherein a pass band of the third filter circuit is about 832 MHz to about 862 MHz (Para [0047], “passband of acoustic wave filter 30 may also include…4G LTE band 20(the transmission band: 832 MHz to 862 MHz)”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the pass band of Mori in the third filter circuit of Yasuda and Goto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., utilizing a filter of a multiplexer within a desired frequency range for its associated application], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/ Examiner, Art Unit 2842
/LINCOLN D DONOVAN/ Supervisory Patent Examiner, Art Unit 2842