DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, 11, & 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2018149580A hereafter referred to as Iwata.
In regards to claim 1, Iwata discloses
An electronic component structure, comprising:
a first electronic component (16 – fig. 1; first paragraph of [Multi-layer sheet for bonding] section);
a second electronic component (17 – fig. 1; first paragraph of [Multi-layer sheet for bonding] section);
a low melting point layer (12 – fig. 1; first paragraph of [Multi-layer sheet for bonding] section) located between the first electronic component and the second electronic component and containing a first metal material having a melting point of 300°C or lower; and
a high melting point layer (11 and/or 13 – fig. 1; first paragraph of [Multi-layer sheet for bonding] section) located between the first electronic component and the second electronic component and containing a second metal material having a melting point of 400°C or higher, wherein
the first electronic component and the second electronic component are connected to each other by a multilayer connection portion formed by overlapping the low melting point layer and the high melting point layer (fig. 1).
In regards to claim 5, Iwata discloses
The electronic component structure according to claim 1, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component (first paragraph of [Multi-layer sheet for bonding] section).
In regards to claim 7, Iwata discloses
The electronic component structure according to claim 1, wherein the multilayer connection portion includes a stacked structure of three or more layers with one high melting point layer sandwiched between two low melting point layers (fig. 1).
In regards to claim 11, Iwata discloses
The electronic component structure according to claim 1, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component (first paragraph of [Multi-layer sheet for bonding] section), and
the high melting point layer (11) contains the first metal material at a content ratio smaller than that of the low melting point layer (first paragraph of [Multi-layer sheet for bonding] section).
In regards to claim 15, Iwata discloses
The electronic component structure according to claim 1, wherein an average thickness of the low melting point layer is 10 μm to 60 μm (third paragraph of [Multi-layer sheet for bonding] section).
Claim(s) 2, 6, 8, & 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2007019360A hereafter referred to as Taniguchi.
In regards to claim 2, Taniguchi discloses
An electronic component structure, comprising:
a first electronic component (20 – fig. 2; [0030]);
a metal plate (11 – fig. 2; [0030]);
a low melting point layer (31 and/or 32 – fig. 2; [0030]) located between the first electronic component and the metal plate and containing a first metal material having a melting point of 300°C or lower; and
a high melting point layer (33 – fig. 2; [0049]) located between the first electronic component and the metal plate and containing a second metal material having a melting point of 400°C or higher, wherein
the first electronic component and the metal plate are connected to each other by a multilayer connection portion formed by overlapping the low melting point layer and the high melting point layer (fig. 2).
In regards to claim 6, Taniguchi discloses
The electronic component structure according to claim 2, wherein the first metal material is Sn alone or a solid solution containing Sn as a main component ([0022]).
In regards to claim 8, Taniguchi discloses
The electronic component structure according to claim 2, wherein the multilayer connection portion includes a stacked structure of three or more layers with one high melting point layer sandwiched between two low melting point layers (fig. 2).
In regards to claim 12, Taniguchi discloses
The electronic component structure according to claim 2, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0022]), and
the high melting point layer contains the first metal material at a content ratio smaller than that of the low melting point layer ([0022] – noting the high melting point layer is Cu, Ni, or Au and is silent to having any Sn (i.e. has less Sn than the low melting point layer)).
Claim(s) 1-8 & 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noguchi (US 2018/0297152).
In regards to claim 1, Noguchi ‘152 discloses
An electronic component structure, comprising:
a first electronic component (14a is a busbar of an electronic component and thus includes the electronic component – fig. 2A & 2B; [0057]);
a second electronic component (14b is a busbar of an electronic component and thus includes the electronic component – fig. 2A & 2B; [0057]);
a low melting point layer (11 – fig. 2A & 2B; [0049]) located between the first electronic component and the second electronic component and containing a first metal material having a melting point of 300°C or lower; and
a high melting point layer (12 or 12 & 15 – fig. 2A & 2B; [0052] & [0063]) located between the first electronic component and the second electronic component and containing a second metal material having a melting point of 400°C or higher, wherein
the first electronic component and the second electronic component are connected to each other by a multilayer connection portion formed by overlapping the low melting point layer and the high melting point layer (fig. 2A & 2B).
In regards to claim 2, Noguchi ‘152 discloses
An electronic component structure, comprising:
a first electronic component(14a is a busbar of an electronic component and thus includes the electronic component – fig. 2A & 2B; [0057]);
a metal plate (14b is a metal busbar (i.e. metal plate) – fig. 2A & 2B; [0057]);
a low melting point layer (11 – fig. 2A & 2B; [0049]) located between the first electronic component and the metal plate and containing a first metal material having a melting point of 300°C or lower; and
a high melting point layer (12 or 12 & 15 – fig. 2A & 2B; [0052] & [0063]) located between the first electronic component and the metal plate and containing a second metal material having a melting point of 400°C or higher, wherein
the first electronic component and the metal plate are connected to each other by a multilayer connection portion formed by overlapping the low melting point layer and the high melting point layer (fig. 2A & 2B).
In regards to claim 3, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein the second metal material comprises an intermetallic compound (15 – fig. 2B; [0063]).
In regards to claim 4, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein the second metal material comprises an intermetallic compound (15 – fig. 2B; [0063]).
In regards to claim 5, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0049]).
In regards to claim 6, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein the first metal material is Sn alone or a solid solution containing Sn as a main component ([0049]).
In regards to claim 7, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein the multilayer connection portion includes a stacked structure of three or more layers with one high melting point layer sandwiched between two low melting point layers (fig. 2A & 2B).
In regards to claim 8, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein the multilayer connection portion includes a stacked structure of three or more layers with one high melting point layer sandwiched between two low melting point layers (fig. 2A & 2B).
In regards to claim 11, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0049]), and
the high melting point layer contains the first metal material at a content ratio smaller than that of the low melting point layer (fig. 2A; [0052] – no Sn contained therein).
In regards to claim 12, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0049]), and
the high melting point layer contains the first metal material at a content ratio smaller than that of the low melting point layer (fig. 2A; [0052] – no Sn contained therein).
In regards to claim 13, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0049]), and
the high melting point layer contains the second metal material which is an intermetallic compound (15), the first metal material (portion of 11 formed at center region in thickness direction in line with 12/15 – fig. 2B and/or Sn contained in intermetallic compound), and a third metal material (12) comprising Cu alone or a solid solution containing Cu as a main component.
In regards to claim 14, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein the first metal material comprises Sn alone or a solid solution containing Sn as a main component ([0049]), and
the high melting point layer contains the second metal material which is an intermetallic compound (15), the first metal material (portion of 11 formed at center region in thickness direction in line with 12/15 – fig. 2B and/or Sn contained in intermetallic compound), and a third metal material (12) comprising Cu alone or a solid solution containing Cu as a main component.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi ‘152.
In regards to claim 15, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein an average thickness of the low melting point layer is 10 μm to 60 μm ([0049]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990)
In regards to claim 16, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein an average thickness of the low melting point layer is 10 μm to 60 μm ([0049]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990)
In regards to claim 17, Noguchi ‘152 discloses
The electronic component structure according to claim 1, wherein an average thickness of the high melting point layer is 30 μm to 100 μm ([0052]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990)
In regards to claim 18, Noguchi ‘152 discloses
The electronic component structure according to claim 2, wherein an average thickness of the high melting point layer is 30 μm to 100 μm ([0052]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990)
Allowable Subject Matter
Claim(s) 9-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest (in combination with the other claim limitations) wherein the high melting point layer comprises a center portion disposed in a center in a first direction perpendicular to a stacking direction of the multilayer connection portion, and peripheral portions disposed on both sides of the center portion so as to sandwich the center portion along the first direction and having a thickness larger than that of the center portion, and the low melting point layers are continuously in contact with the high melting point layer from one of the peripheral portions sandwiching the center portion to the other of the peripheral portions via the center portion (claims 9-10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2014/0077376 – fig. 3 US 2017/0232562 – fig. 5
JP2019135734A – fig. 2 CN106378583A – fig. 1
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2848