DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 13 and 14 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons. Pending claims 1, 3-5, 7, 9, 10, and 12, Invention I, are drawn to a solar cell while newly added claims 13 and 14, Invention II, are drawn to a method of making a solar cell. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the product as claimed can be made by another and materially different process. For example pending claims 1, 3-5, 7, 9, 10, and 12, Invention I can be made wherein the first and second semiconductor layers are stacked before the anisotropic etching.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 13 and 14 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 4, 5, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toshihiko (JP 2014229876 A, mapped to translation provided on 01/08/2025).
Regarding claims 1 and 4, Toshihiko discloses a solar cell, comprising (see Figs. 1, 3 and 7, [0058]):
a semiconductor substrate (1); and
a first semiconductor layer (3a) having first conductivity and stacked on a first main surface (front surface) of the semiconductor substrate and a second semiconductor layer (3b) having second conductivity and stacked on a second surface (rear surface) of the semiconductor substrate that is different than the first main surface.
In addition, Toshihiko discloses a silicon substrate with a concave-convex structure wherein the convex portions are rounded to suppress defects and pinholes ([0042]-[0055]) and also discloses these dimension serve to reduce reflectance (Fig. 3, [0042]-[0045][0055][0109]).
However, Toshihiko does not explicitly disclose wherein a material volume Vmp at 10% of an areal material ratio of at least the first main surface of the semiconductor substrate is from 0.003 μm3/μm2 to 0.010 μm3/μm2.
Applicant’s specification indicates that the claimed dimensions serve to reduce reflectance and prevent pinhole formation (see [0023] of US2024/0224550 A1 a publication of instant application).
Furthermore, Toshihiko discloses the same process of anisotropic etching (claim 1) which Applicant has described as achieving the above claimed dimensions and Toshihiko discloses additional steps of mechanical polishing may also be used to achieve the dimensions required of r1 relative to r2 ([0051]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the dimension of r1 relative to r2 of modified Toshihiko so that the claimed dimensions are present because Toshihiko discloses that doing so allows for a reduction in reflectance and a suppression of defects in subsequent layer growth.
Regarding claims 5 and 10, modified Toshihiko discloses all of the claim limitations as set forth above.
In addition Toshihiko discloses a texture structure having a plurality of pyramidal projections on a second main surface of the semiconductor substrate (see Fig. 7c, [0074][0075]).
Claim(s) 3, 7, 9, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toshihiko (JP 2014229876 A, mapped to translation provided on 01/08/2025) as applied to claims 1, 4, 5, and 10 above and in further view of Kim (US 2020/0212243 A1).
Regarding claims 3 and 7, modified Toshihiko discloses all of the claim limitations as set forth above.
However, Toshihiko does not disclose an organic photoelectric conversion layer stacked on a side of the first main surface and comprising a perovskite compound.
Kim discloses that on top of a silicon solar cell substrate and silicon emitter layer (111-113, [0049]) an interlayer formed of a transparent conductive oxide (114) can be placed and on top of the interlayer a perovskite solar cell (120 [0038], see Fig. 3 [0050]-[0052]) can be stacked and in this tandem configuration allows for both long and short wavelength light to be absorbed ([0036]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the silicon solar cell of modified Toshihiko by removing the top contact layers which include, 6a, 9, 71 and 72 and adding the perovskite solar cell and interlayer as disclosed by Kim because Kim discloses that this allow for both long and short wavelength light to be absorbed.
Regarding claims 9 and 12, modified Toshihiko discloses all of the claim limitations as set forth above.
In addition Toshihiko discloses a texture structure having a plurality of pyramidal projections on a second main surface of the semiconductor substrate (see Fig. 7c, [0074][0075]).
Response to Arguments
Applicant respectfully contends that the material volume Vmp of the present claims is in a range that can be realized reliably by polishing by chemical mechanical polishing as employed in the embodiments. In contrast, the embodiments of Toshihiko employ only wet etching; therefore, Toshihiko intends a range of shapes obtained by wet etching. While Toshihiko describes in [0051] as "using any one method among a wet chemical etching method, a dry chemical etching method, an electrochemical etching method, and a mechanical etching method," this description only suggests the possibility of alternatives to wet etching and never extends the target shape obtained by wet etching to a shape obtained by mechanical etching. Accordingly, Toshihiko never suggests "a material volume Vmp at 10% of an areal material ratio of at least the first main surf ace of the semiconductor substrate is from 0.003 μm3/μm2 to 0.010 μm3/μm2," as recited in independent claim 1.
Toshihiko discloses additional steps of mechanical polishing may also be used to achieve the dimensions required of r1 relative to r2 ([0051]) and that adjusting r1 and r2 to be within a range of values suppresses pinhole formation and also suppresses the increase in substrate reflectance ([0042]-[0055][0079][0082]). Therefore Toshihiko provides motivation to have the claimed range of Vmp to optimize suppression of pinhole formation and also suppression of the increase in substrate reflectance. Applicant’s specification discloses that achieving the claimed Vmp serves to reduce reflectance and prevent pinhole formation which is the same aim as Toshioko.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 517-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/ Primary Examiner, Art Unit 1726
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