DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 4-6, 8, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toshihiko (JP 2014229876 A, mapped to translation provided on 01/08/2025).
Regarding claims 1, 2, 4, and 6, Toshihiko discloses a solar cell, comprising (see Figs. 1, 3 and 7, [0058]):
a semiconductor substrate (1); and
a first semiconductor layer (3a) having first conductivity and a second semiconductor layer (3b) having second conductivity that are stacked on the semiconductor substrate.
In addition, Toshihiko discloses a silicon substrate with a concave-convex structure wherein the convex portions are rounded to suppress defects and pinholes ([0042]-[0055]) and also discloses these dimension serve to reduce reflectance (Fig. 3, [0042]-[0045][0055][0109]).
However, Toshihiko does not explicitly disclose wherein a material volume Vmp at 10% of an areal material ratio of at least a first main surface of the semiconductor substrate is from 0.003 μm3/μm2 to 0.010 μm3/μm2.
Applicant’s specification indicates that the claimed dimensions serve to reduce reflectance and prevent pinhole formation (see [0023] of US2024/0224550 A1 a publication of instant application).
Furthermore, Toshihiko discloses the same process of anisotropic etching (claim 1) which Applicant has described as achieving the above claimed dimensions and Toshihiko discloses additional steps of mechanical polishing may also be used to achieve the dimensions required of r1 relative to r2 ([0051]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the dimension of r1 relative to r2 of modified Toshihiko so that the claimed dimensions are present because Toshihiko discloses that doing so allows for a reduction in reflectance and a suppression of defects in subsequent layer growth.
Regarding claims 5, 8, 10, and 11, modified Toshihiko discloses all of the claim limitations as set forth above.
In addition Toshihiko discloses a texture structure having a plurality of pyramidal projections on a second main surface of the semiconductor substrate (see Fig. 7c, [0074][0075]).
Claim(s) 3, 7, 9, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toshihiko (JP 2014229876 A, mapped to translation provided on 01/08/2025) as applied to claims 1, 2, 4-6, 8, 10, and 11 above and in further view of Kim (US 2020/0212243 A1).
Regarding claims 3 and 7, modified Toshihiko discloses all of the claim limitations as set forth above.
However, Toshihiko does not disclose an organic photoelectric conversion layer stacked on a side of the first main surface and comprising a perovskite compound.
Kim discloses that on top of a silicon solar cell substrate and silicon emitter layer (111-113, [0049]) an interlayer formed of a transparent conductive oxide (114) can be placed and on top of the interlayer a perovskite solar cell (120 [0038], see Fig. 3 [0050]-[0052]) can be stacked and in this tandem configuration allows for both long and short wavelength light to be absorbed ([0036]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the silicon solar cell of modified Toshihiko by removing the top contact layers which include, 6a, 9, 71 and 72 and adding the perovskite solar cell and interlayer as disclosed by Kim because Kim discloses that this allow for both long and short wavelength light to be absorbed.
Regarding claims 9 and 12, modified Toshihiko discloses all of the claim limitations as set forth above.
In addition Toshihiko discloses a texture structure having a plurality of pyramidal projections on a second main surface of the semiconductor substrate (see Fig. 7c, [0074][0075]).
Response to Arguments
Applicant argues Toshihiko does not describe or suggest a post process after etching.
Toshihiko discloses additional steps of mechanical polishing may also be used to achieve the dimensions required of r1 relative to r2 ([0051]).
Applicant argues that the SEM images illustrate a range of shapes for the texture within the range of the material volume Vmp in the claimed range, and that these shapes cannot be made by Toshihiko's process. SEM images of surfaces at the Vmp upper limit and Vmp lower limit according to the present disclosure.
Toshioko discloses that adjusting r1 and r2 to be within a range of values suppresses pinhole formation and also suppresses the increase in substrate reflectance ([0042]-[0055][0079][0082]). There is motivation provided by Toshioko to achieve the claimed Vmp, since achieving the claimed Vmp according to Applicant’s specification serve to reduce reflectance and prevent pinhole formation which is the same aim as Toshioko.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 517-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/ Primary Examiner, Art Unit 1726