Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 13, 2024 and April 1, 2025 are in compliance with time for filing requirements of 3 7 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 19 recites the limitation “an uppermost surface [WC] of the first power rail [FSR] is at least twice as wide as an uppermost surface [WU] of the second power rail [BSR] …”, this limitation conflicts with paragraph 0025 of the specification and Fig. 2. Specifically, the following sections: “power rail FSR may be narrower, in the X-direction, than the power rail BSR”, “a width WU of an uppermost surface of the power rail BSR may be at least double…a width WC of the power rail FSR”, and “lowermost width WL [of the power rail BSR] may be wider than (e.g., at least 50% wider, or even at least double) the constant width WC, and the uppermost width WU may be at least twice as wide as the constant width WC”.
Regarding the specification, the examiner interprets the claim to instead read as “an uppermost surface [WU] of the second power rail [BSR] is at least twice as wide as the width [WC] of the first power rail [FSR]”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (US20230062140A1).
Regarding Claim 1:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2):
a vertical transistor stack (Fig. 1A element 101, paragraphs 27 and 30) that comprises a first transistor having a first conductivity type (Fig. 1A element 104, paragraph 30) and a second transistor having a second conductivity type that is opposite from the first conductivity type (Fig. 1A element 102, paragraph 30), the first transistor arranged to overlap the second transistor (paragraph 30) in a vertical direction (Z-direction; Fig. 1A); and
a dual power rail (Fig. 1A elements 105A and 118) comprising a first power rail (element 107A) and a second power rail (element 120) that are on opposite sides of the first transistor (element 104) in the vertical direction (Z-direction) and configured to provide respective power signals to the first transistor (paragraphs 30 and 38).
Regarding Claim 2:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, wherein the first transistor (element 104) is a PMOS transistor and the second transistor (element 102) is a NMOS transistor (paragraph 35).
Regarding Claim 3:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, wherein the first power rail (Fig. 4C element 462) has a first width (3H-7H; paragraph 139), and wherein the second power rail (Fig. 4C element 472) has a second width that is wider than the first width (6H-9H; paragraph 139).
Regarding Claim 4:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, wherein the CMOS device (Fig. 1A element 100A) further comprises a signal line (Fig. 1A element 109A/B) that is configured to transmit a data signal (paragraph 30) and on a side of the first transistor (element 104) in common with the first power rail (Fig. 1A elements 107A and 109A/B, paragraph 34).
Regarding Claim 6:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, further comprising a first frontside metal line and a second frontside metal line (Fig. 4 elements 405B, 409, 412, paragraphs 132-147), wherein the first power rail is an inner rail (Fig. 4 elements 407) that is arranged in a horizontal direction (Y-direction) between the first frontside metal line and the second frontside metal line (Fig. 4 elements 409 and 412, respectively).
Regarding Claim 7:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, further comprising a first power source (supply voltage VDD) and a second power source (supply voltage VSS) that are coupled (paragraphs 36 and 38) to the first transistor (Fig. 1A element 104) via the first power rail (element 107A) and the second power rail (element 120), respectively.
Regarding Claim 11:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 7, wherein the second power rail is a first backside power rail (Fig. 4C element 420C, paragraphs 20, 143, and 173), and wherein the CMOS device (Fig. 4 element 400F) further comprises a second backside power rail (Fig. 4C element 420D, paragraphs 20 143, and 173) that is coupled to the second power source (paragraphs 138-139 and 143).
Regarding Claim 12:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device comprising (Figs. 1A and 4A-C, paragraph 2) according to claim 1, wherein the first transistor (Fig. 1A element 104) comprises a first source/drain (S/D) region (Fig. 1A element 130A) and a second S/D region (Fig. 1A element 114A), and wherein the first power rail (element 107A) and the second power rail (element 120) are both coupled to the first S/D region of the first transistor (via and MDLI; Fig. 1A elements 126, 138, 128A, paragraph 44).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US20230062140A1) in view of Wang et al. (US20220359493A1).
Regarding Claim 5:
Lai discloses a CMOS device (Figs. 1A and 4A-C, paragraph 2) according to claim 1, wherein the first power rail (element 107A) is configured to transmit a power signal having a first voltage (VDD; paragraphs 36-38), and wherein the second power rail (element 120) is configured to transmit a power signal having a second voltage (VSS; paragraphs 36-38). Lai, however, does not explicitly teach the second power rail with the power signal having a second voltage higher than the first voltage.
Wang discloses an analogous integrated circuit (Fig. 1B element IC1) with a first power rail (element VDD) and a second power rail (element VSS), wherein the second power rail is configured to transmit a power signal having a second voltage higher than the first voltage (paragraphs 21-22 and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the device described in Lai further in view of Wang such that the second power rail is configured to transmit a power signal having a second voltage that is higher than the first voltage of the first power rail because both are directed to analogous CMOS devices. Doing so allows for improvements in power grid distribution and routing flexibility (Wang, paragraphs 39-40).
Regarding Claim 8:
Lai discloses a CMOS device (Figs. 1A and 4A-C, paragraph 2) according to claim 7, wherein the first power source comprises a first power source configured to provide a first power signal having a first voltage (VDD; paragraphs 36-38), and wherein the second power source comprises a second power source configured to provide a second power signal having a second voltage (VSS; paragraphs 36-38). Lai, however does not explicitly teach the second power source with the second power signal having a second voltage higher than the first voltage.
Wang discloses an analogous integrated circuit (Fig. 1B element IC1) with a first power source (element VDD) and a second power source (element VSS), wherein the second power source is configured to provide a second power signal having a second voltage higher than the first voltage (paragraphs 21-22 and 44)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the device described in Lai further in view of Wang such that the second power source is configured to transmit a second power signal having a second voltage that is higher than the first voltage of the first power source because both are directed to analogous CMOS devices. Doing so allows for improvements in power grid distribution and routing flexibility (Wang, paragraphs 39-40).
Claims 9-10, 13-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US20230062140A1) in view of Doornbos et al. (US20210098361A1).
Regarding Claim 9:
Lai discloses a CMOS device (Figs. 1A and 4A-C, paragraph 2) according to claim 7, but does not explicitly teach a first power source that is configured to be active while a second power source is inactive, and vice versa.
Doornbos, however, discloses an analogous semiconductor device (Figs. 1-4) wherein the first power source (Fig. 2A element VDD) is configured to be active while the second power source (Fig. 2A element VVDD) is inactive, and vice versa (paragraphs 22-23 and 52).
It would have been obvious before the effective filing date of the claimed invention to modify the device described in Lai further in view of Doornbos to such that a first power source can be configured to be active while the second power source is inactive, and vice versa, because both are directed to analogous CMOS devices. Doing so allows for the minimization of power consumption in semiconductor devices while allowing for an increase in package density (Doornbos, paragraphs 21 and 52).
Regarding Claim 10:
The combination of Lai and Doornbos discloses a CMOS device according to claim 9, but Lai does not explicitly teach a controller that is coupled to a first and second power source. Nor does Lai teach where the controller is configured to activate the first power source while second power source is inactive, and vice versa.
Doornbos, however, discloses a controller (switch; paragraphs 22-23 and 52) that is coupled to both the first power source (Fig. 2A element VDD) and the second power source (Fig. 2A element VVDD), wherein the controller is configured to activate the first power source while the second power source is inactive (paragraphs 22-23 and 52), and wherein the controller is further configured to activate the second power source while the first power source is inactive (paragraphs 22-23 and 52).
It would have been obvious before the effective filing date of the claimed invention to modify the device described in Lai further in view of Doornbos to include a controller coupled and configured to activate a first power source while a second power source is inactive, and vice versa, because both are directed to analogous CMOS devices. Doing so allows for the minimization of power consumption in semiconductor devices while allowing for an increase in package density (Doornbos, paragraphs 21 and 52).
Regarding Claim 13:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device (Figs. 1A and 4, paragraph 2) comprising:
a substrate (Fig. 1A and 4 element 460, paragraph 30) comprising a PMOS transistor (elements 104/404) and an NMOS transistor (elements 102/402);
a first power rail (elements 107/407) and a second power rail (elements 120/420) that are both coupled (vias; Figs. 1A and 4, paragraphs 30, 34, 38, and 128) to the PMOS transistor and arranged on opposite sides of the PMOS transistor in a vertical direction (Z-direction),
a first power source (supply voltage VDD) and a second power source (supply voltage VSS) that are coupled (paragraphs 36 and 38) to the PMOS transistor (Fig. 1A element 104) via the first power rail (element 107A) and the second power rail (element 120), respectively.
Lai discloses a first and second power source (VDD and VSS, respectively) but does not explicitly teach a controller that is coupled to a first and second power source. Nor does Lai teach where the controller is configured to activate the first power source while second power source is inactive, and vice versa.
Doornbos, however, discloses a controller (switch; paragraphs 22-23 and 52) that is coupled to the first power source (Fig. 2A element VDD) and the second power source (Fig. 2A element VVDD), wherein the controller is configured to activate the first power source while the second power source is deactivated (paragraphs 22-23 and 52, and wherein the controller is further configured to activate the second power source while the first power source is deactivated (paragraphs 22-23 and 52).
It would have been obvious before the effective filing date of the claimed invention to modify the device described in Lai further in view of Doornbos to include a controller coupled and configured to activate a first power source while a second power source is deactivated, and vice versa, because both are directed to analogous CMOS devices. Doing so allows for the minimization of power consumption in semiconductor devices while allowing for an increase in package density (Doornbos, paragraphs 21 and 52).
Regarding Claim 14:
The combination of Lai and Doornbos discloses a semiconductor device according to claim 13, wherein Lai discloses the PMOS transistor and the NMOS transistor are arranged to overlap each other in the vertical direction (Z-direction; Fig. 1A elements 104 and 102, respectively).
Regarding Claim 15:
The combination of Lai and Doornbos discloses a semiconductor device according to claim 13, wherein Lai discloses the PMOS transistor and the NMOS transistor are arranged to overlap each other in a horizontal direction (Y-direction; Fig. 4 elements 404 and 402, respectively).
Regarding Claim 17:
The combination of Lai and Doornbos discloses a semiconductor device according to claim 13, wherein Lai further discloses a third power rail (Fig. 4 element 420D) arranged to overlap the second power rail (element 420C) in a horizontal direction (Y-direction).
Regarding Claim 18:
Lai discloses a complementary metal–oxide–semiconductor (CMOS) device (Figs. 1A and 4, paragraph 2) comprising:
a vertical transistor stack (Fig. 1A element 101, paragraph 27 and 30) that that includes a first transistor (Fig. 1A element 104) and a second transistor (Fig. 1A element 102) arranged to overlap (paragraph 30) each other in a vertical direction (Z-direction; Fig. 1A);
a first power source (supply voltage VDD) and a second power source (supply voltage VSS) that are both coupled (paragraphs 36 and 38) to the first transistor and configured to provide respective first (VDD; Fig. 1A element 107A, paragraphs 36-38 and 125) and second power signals to the first transistor (VSS; Fig. 1A element 120, paragraphs 36-38 and 128).
Lai discloses a first and second power source (VDD and VSS, respectively) but does not explicitly teach a controller that is coupled to a first and second power source. Nor does Lai teach where the controller is configured to turn on the first power source while second power source is turned off, and vice versa.
Doornbos, however, discloses a controller (switch; paragraphs 22-23 and 52) that is coupled to both the first power source (Fig. 2A element VDD) and the second power source (Fig. 2A element VVDD), wherein the controller is configured to turn on the first power source while the second power source is turned off (paragraphs 22-23 and 52), and wherein the controller is further configured to turn on the second power source while the first power source is turned off (paragraphs 22-23 and 52).
It would have been obvious before the effective filing date of the claimed invention to modify the device described in Lai further in view of Doornbos to include a controller coupled and configured to turn on a first power source while a second power source is turned off, and vice versa, because both are directed to analogous CMOS devices. Doing so allows for the minimization of power consumption in semiconductor devices while allowing for an increase in package density (Doornbos, paragraphs 21 and 52).
Regarding Claim 19:
The combination of Lai and Doornbos discloses a semiconductor device according to claim 18, wherein Lai further discloses:
a first power rail (Fig. 1A element 107A) that is coupled (vias; paragraph 34) between the first power source and the first transistor (Fig. 1A element 104); and
a second power rail (Fig. 1A element 120) that is coupled (vias; paragraph 34) between the second power source and the first transistor (Fig. 1A element 104),
wherein an uppermost surface of the first power rail is at least twice as wide as an uppermost surface of the second power rail (Fig. 4 elements 462 and 472, paragraph 139), and
wherein the first (Fig. 1A element 107A) and second power rails are (Fig. 1A element 120) on opposite sides of the first transistor (Fig. 1A element 104) in the vertical direction (Z-direction).
Regarding Claim 20:
The combination of Lai and Doornbos discloses a semiconductor device according to claim 19, wherein Lai discloses the first transistor is closer to the first power rail than to the second power rail (Fig. 1A).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US20230062140A1) in view of Doornbos et al. (US20210098361A1) as applied to claim 13 above, and further in view of Wang et al. (US20220359493A1).
Regarding Claim 16:
The combination of Lai and Doornbos discloses a CMOS device according to claim 13, wherein the first power rail (Lai: Fig. 1A element 107/407) is configured to supply a first power signal having a first voltage (VDD; paragraphs 36-38 and 125), wherein the second power rail (element 120/420) is configured to supply a second power signal having a second voltage (VSS; paragraphs 36-38 and 128), and wherein the first power rail is narrower than the second power rail (Fig. 4 elements 462 and 472, paragraph 139). However, neither Lai nor Doornbos explicitly teach a second power source with a second power signal having a second voltage higher than the first voltage.
Wang discloses an analogous integrated circuit (Fig. 1B element IC1) with a first power source (element VDD) and a second power source (element VSS), wherein the second power source is configured to provide a second power signal having a second voltage higher than the first voltage (paragraphs 21-22 and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the device described in Lai and Doornbos further in view of Wang such that the second power source is configured to supply a second power signal having a second voltage that is higher than the first voltage of the first power source because both are directed to analogous CMOS devices. Doing so allows for improvements in power grid distribution and routing flexibility (Wang, paragraphs 39-40).
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai et al. (US 12431428 B2).
Conclusion
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/Chloë E Benton/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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