DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 16 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Failure to narrow base claim. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20200082987) in view of Park et al. (US20200051739) and Iguchi et al. (US20220165502).
With respect to claim 1, Lee teaches a multilayer electronic component (see FIG. 1, element 100), comprising: a body (see FIG. 1, element 110) including a dielectric layer (see FIG. 2, element 111) and internal electrodes (see FIG. 2, elements 121 and 122) disposed alternately with the dielectric layer in a first direction (see FIG. 1, Z direction), and including first (see FIG. 1, element 1) and second surfaces (see FIG. 1, element 2) opposing each other in the first direction, third (see FIG. 1, element 3) and fourth surfaces (see FIG. 1, element 4) connected to the first and second surfaces and surfaces opposing each other in a second direction (see FIG. 1, X direction), and fifth (see FIG. 1, element 5) and sixth surfaces (see FIG. 1, element 6) connected to the first to fourth surfaces and surfaces opposing each other in a third direction (see FIG. 1, Y direction); a first side margin portion (see FIG. 3, element 111) disposed on the fifth surface; a second side margin portion (see FIG. 3, element 111) disposed on the sixth surface; a first external electrode (see FIG. 1, element 131) disposed on the third surface; and a second external electrode (see FIG. 1, element 132) disposed on the fourth surface, and wherein, when an average size of the body in the first direction is defined as T0, 100 µm < (W0 +T0)/2 < 250 µm is satisfied (see paragraph 84, noting (200+200)/2 = 200 which satisfied the claim limitation).
Lee does not expressly teach that when an average size of the first side margin portion in the third direction is defined as W1, an average size of the second side margin portion in the third direction is defined as W2, and an average size in the third direction from an external surface of the first side margin portion to an external surface of the second side margin portion is defined as W0, (W1 + W2) / W0 < 0.20 is satisfied, and wherein, when an average thickness of the dielectric layer is defined as td and an average thickness of the internal electrodes is defined as te.
Park, on the other hand, teaches when an average size of the first side margin portion in the third direction is defined as W1, an average size of the second side margin portion in the third direction is defined as W2, and an average size in the third direction from an external surface of the first side margin portion to an external surface of the second side margin portion is defined as W0, (W1 + W2) / W0 < 0.20 is satisfied (see paragraph 38 in combination with paragraph 159, noting (10+10)/300 = 0.066 which satisfied the claim limitation), and wherein, when an average thickness of the dielectric layer is defined as td and an average thickness of the internal electrodes is defined as te (see paragraph 134, noting td as thickness of a dielectric layer and te as thickness of an internal electrode) but fails to teach that te > td is satisfied. As such, it would be obvious to one of ordinary skill in the art before the effective filling date of the claim invention, to use average size of the side margins portions of Park with the capacitor of Lee for securing insulation properties (see Park paragraph 80).
Iguchi, on the other hand, teaches te > td is satisfied (see paragraph 37, noting an average thickness (ATe) of the internal electrode layers 12 is preferably thicker than an average thickness (ATd) of the dielectric layers 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use an average thickness of the internal electrode layers and the dielectric layers of Iguchi with the capacitor of Lee and Park for the purpose to suppressed crack formation and increased a capacitance (see Iguchi paragraph 38).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park and Iguchi to form the claimed invention in order to suppressed crack formation and increased a capacitance (see Iguchi paragraph 38).
With respect to claim 2, the combined teachings of Lee, Park and Iguchi teach that a first cover portion disposed on one surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and a second cover portion disposed on another surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and wherein, when an average size of the first cover portion in the first direction is defined as T1, an average size of the second cover portion in the first direction is defined as T2, and an average size of the body in the first direction is defined as T0, (T1+ T2) / T0 < 0.23 is satisfied (see Park paragraph 57 in combination with paragraph 159, noting (20+20)/300 = 0.133 which satisfied the claim limitation).
With respect to claim 4, the combined teachings of Lee, Park and Iguchi teach that the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see Lee FIG. 2, elements 111, 121 and 122, paragraph 22), a first cover portion disposed on one surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and a second cover portion disposed on another surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and wherein, when an average size of the first cover portion in the first direction is defined as T1 and an average size of the second cover portion in the first direction is defined as T2, 5 μm < (W1 + W2) / 2 < (T1+ T2) / 2 is satisfied (see Park paragraphs 38 and 57, noting 5 μm < (10 + 10) / 2 = 10 < (20 + 20) / 2 = 20 which satisfied the claim limitation).
With respect to claim 9, the combined teachings of Lee, Park and Iguchi teach that when a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in an outermost portion in the first direction among the internal electrodes, is defined as tc2 (see Park FIG. 4, element tc2) and a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in a central portion in the first direction among the internal electrodes, is defined as tc1 (see Park FIG. 4, element tc1), a ratio tc2/tc1 is 0.9 or more and 1.0 or less (see Park paragraphs 110 and 111, noting a ratio of a thickness tc2 to a thickness tc1 may be 0.9 or more and 1.0 or less).
With respect to claim 10, the combined teachings of Lee, Park and Iguchi teach that when a thickness of the first or second side margin portion in contact with an edge of the body is defined as tc3 (see Park FIG. 4, element tc3) and a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in a central portion in the first direction among the internal electrodes, is defined as tc1 (see Park FIG. 4, element tc1), a ratio tc3/tc1 is 0.9 or more and 1.0 or less (see Park paragraphs 119 and 120, noting a ratio of a thickness tc3 to a thickness tc1 may be 0.9 or more and 1.0 or less).
Claim 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Park and Iguchi, as applied to claim 1 above, and further in view of An et al. (US20220270824).
With respect to claim 5, Lee, Park and Iguchi teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 1, wherein the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see Lee FIG. 2, elements 111, 121 and 122, paragraph 22), a first cover portion disposed on one surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and a second cover portion disposed on another surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36).
Lee, Park and Iguchi do not teach wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second cover portions is defined as G1, 1 < G1/G0 < 1.3 is satisfied.
An, on the other hand, teaches wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 2, element 111, paragraph 37, noting Gc is a central region of the capacitance formation portion), and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second cover portions is defined as G1 (see FIG. 2, element 120, paragraph 37, noting Gm is an outer region of the capacitance formation portion 120), 1 < G1/G0 < 1.3 is satisfied (see paragraph 37, noting a ratio of Gm/Gc may be less than 1.3).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and An to form the claimed invention in order to improve reliability of a multilayer ceramic electronic component (see An paragraph 60).
With respect to claim 6, Lee, Park and Iguchi teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 1, wherein the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see Lee FIG. 2, elements 111, 121 and 122, paragraph 22).
Lee, Park and Iguchi do not teach wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second side margin portions is defined as G2, 0.9 < G2/G0 < 1.3 is satisfied.
An, on the other hand, teaches wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 2, element 111, paragraph 37, noting Gc is a central region of the capacitance formation portion), and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second side margin portions is defined as G2 (see FIG. 2, element 120, paragraph 37, noting Gm is an outer region of the capacitance formation portion 120), 0.9 < G2/G0 < 1.3 is satisfied (see paragraph 37, noting a ratio of Gm/Gc may be less than 1.3).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and An to form the claimed invention in order to improve reliability of a multilayer ceramic electronic component (see An paragraph 60).
Claim 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Park and Iguchi, as applied to claim 1 above, and further in view of Kaneko et al. (US20160293333).
With respect to claim 7, Lee, Park and Iguchi teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 1, wherein the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see Lee FIG. 2, elements 111, 121 and 122, paragraph 22).
Lee, Park and Iguchi do not teach wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 and an average grain size of the dielectric layer in a central region of the first and second side margin portions is defined as G3, 1 < G3/G0 < 1.3 is satisfied.
Kaneko, on the other hand, teaches wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 1, element 14, paragraph 48, noting the capacitance region 14 is Di) and an average grain size of the dielectric layer in a central region of the first and second side margin portions is defined as G3 (see FIG. 1, element 16, paragraph 48, noting the side protection region 16 is Dh′), 1 < G3/G0 < 1.3 is satisfied (see paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and Kaneko to form the claimed invention in order to obtain the capacitor with a high capacitance and improve the reliability (see Kaneko paragraph 55).
With respect to claim 8, Lee, Park and Iguchi teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 1, wherein the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see Lee FIG. 2, elements 111, 121 and 122, paragraph 22), a first cover portion disposed on one surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36), and a second cover portion disposed on another surface of the capacitance forming portion in the first direction (see Lee FIG. 2, element 112, paragraph 36).
Lee, Park and Iguchi do not teach wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a central region of the first and second cover portions is defined as G4, 1 < G4/G0 < 1.4 is satisfied.
Kaneko, on the other hand, teaches wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 1, element 14, paragraph 48, noting the capacitance region 14 is Di), and an average grain size of the dielectric layer in a central region of the first and second cover portions is defined as G4 (see FIG. 1, element 11, paragraph 52, noting the exterior area 11 is Dg), 1 < G4/G0 < 1.4 is satisfied (see paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation). It would clearly be well within the per view of a person having ordinary skill Dg/Di to be 1.1 or 1.2 or more to improve reliability.
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and Kaneko to form the claimed invention in order to obtain the capacitor with a high capacitance and improve the reliability (see Kaneko paragraph 55).
Claims 11-13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20200082987) in view of Park et al. (US20200051739), Iguchi et al. (US20220165502) and Kaneko et al. (US20160293333).
With respect to claim 11, Lee teaches a multilayer electronic component, comprising (see FIG. 1, element 100): a body (see FIG. 1, element 110) including a dielectric layer (see FIG. 2, element 111) and internal electrodes (see FIG. 2, elements 121 and 122) disposed alternately with the dielectric layer in a first direction (see FIG. 1, Z direction), and including first (see FIG. 1, element 1) and second surfaces (see FIG. 1, element 2) opposing each other in the first direction, third (see FIG. 1, element 3) and fourth surfaces (see FIG. 1, element 4) connected to the first and second surfaces and surfaces opposing each other in a second direction (see FIG. 1, X direction), and fifth (see FIG. 1, element 5) and sixth surfaces (see FIG. 1, element 6) connected to the first to fourth surfaces and surfaces opposing each other in a third direction (see FIG. 1, Y direction); a first side margin portion (see FIG. 3, element 111) disposed on the fifth surface; a second side margin portion (see FIG. 3, element 111) disposed on the sixth surface; a first external electrode disposed (see FIG. 1, element 131) on the third surface; and a second external electrode (see FIG. 1, element 132) disposed on the fourth surface, wherein the body further includes a capacitance forming portion in which the dielectric layer and the internal electrodes are alternately disposed in the first direction to form capacitance (see FIG. 2, elements 111, 121 and 122, paragraph 22), a first cover portion disposed on one surface of the capacitance forming portion in the first direction (see FIG. 2, element 112, paragraph 36) and a second cover portion (see FIG. 2, element 112, paragraph 36) disposed on another surface of the capacitance forming portion in the first direction.
Lee does not expressly teach that when an average size of the first cover portion in the first direction is defined as T1, an average size of the second cover portion in the first direction is defined as T2, and an average size of the body in the first direction is defined as T0, (T1 + T2) / T0 < 0.23 is satisfied, wherein, when an average thickness of the dielectric layer is defined as td and an average thickness of the internal electrodes is defined as te, te > td is satisfied, and wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a central region of the first side margin portion or the second side margin portion is defined as G3, 1 < G3/G0 < 1.3 is satisfied.
Park, on the other hand, teaches when an average size of the first cover portion in the first direction is defined as T1, an average size of the second cover portion in the first direction is defined as T2, and an average size of the body in the first direction is defined as T0, (T1 + T2) / T0 < 0.23 is satisfied (see paragraph 57 in combination with paragraph 159, noting (20+20)/300 = 0.133 which satisfied the claim limitation), wherein, when an average thickness of the dielectric layer is defined as td and an average thickness of the internal electrodes is defined as te (see paragraph 134, noting td as thickness of a dielectric layer and te as thickness of an internal electrode) but fails to teach that te > td is satisfied, and wherein, when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a central region of the first side margin portion or the second side margin portion is defined as G3, 1 < G3/G0 < 1.3 is satisfied. As such, it would be obvious to one of ordinary skill in the art before the effective filling date of the claim invention, to use average size of the side of the cover portions of Park with the capacitor of Lee for securing insulation properties (see Park paragraph 80).
Iguchi, on the other hand, teaches te > td is satisfied (see paragraph 37, noting an average thickness (ATe) of the internal electrode layers 12 is preferably thicker than an average thickness (ATd) of the dielectric layers 10) but fails to teach and when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a central region of the first side margin portion or the second side margin portion is defined as G3, 1 < G3/G0 < 1.3 is satisfied. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use an average thickness of the internal electrode layers and the dielectric layers of Iguchi with the capacitor of Lee and Park for the purpose to suppressed crack formation and increased a capacitance (see Iguchi paragraph 38).
Kaneko, on the other hand, teaches when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 1, element 14, paragraph 48, noting the capacitance region 14 is Di), and an average grain size of the dielectric layer in a central region of the first side margin portion or the second side margin portion is defined as G3 (see FIG. 1, element 16, paragraph 48, noting the side protection region 16 is Dh′), 1 < G3/G0 < 1.3 is satisfied (see paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation). As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use an average grain size of the dielectric layer in a central region of the capacitance forming portion and an average grain size of the dielectric layer in a central region of the first side margin portion of Kaneko with the capacitor of Lee, Park and Iguchi for the purpose to obtain the capacitor with a high capacitance and improve the reliability (see Kaneko paragraph 55).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and Kaneko to form the claimed invention in order to obtain the capacitor with a high capacitance and improve the reliability (see Kaneko paragraph 55).
With respect to claim 12, the combined teachings of Lee, Park, Iguchi and Kaneko teach that an average size in the third direction from an external surface of the first side margin portion to an external surface of the second side margin portion is defined as W0 and an average size of the body in the first direction is defined as T0, 100 μm < (W0+T0) / 2 < 250 μm is satisfied (see Lee paragraph 84, noting (200+200)/2 = 200 which satisfied the claim limitation).
With respect to claim 13, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when an average size of the first side margin portion in the third direction is defined as W1 and an average size of the second side margin portion in the third direction is defined as W2, 5μm < (W1 + W2) / 2 < (T1 + T2) / 2 is satisfied (see Park paragraphs 38 and 57, noting 5 μm < (10 + 10) / 2 = 10 < (20 + 20) / 2 = 20 which satisfied the claim limitation).
With respect to claim 16, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see Kaneko FIG. 1, element 14, paragraph 48, noting the capacitance region 14 is Di) and an average grain size of the dielectric layer in a central region of the first and second side margin portions is defined as G3 (see Kaneko FIG. 1, element 16, paragraph 48, noting the side protection region 16 is Dh′), 1 < G3/G0 < 1.3 is satisfied (see Kaneko paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation).
With respect to claim 17, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see Kaneko FIG. 1, element 14, paragraph 48, noting the capacitance region 14 is Di), and an average grain size of the dielectric layer in a central region of the first and second cover portions is defined as G4 (see Kaneko FIG. 1, element 11, paragraph 52, noting the exterior area 11 is Dg), 1 < G4/G0 < 1.4 is satisfied (see Kaneko paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation). It would clearly be well within the per view of a person having ordinary skill Dg/Di to be 1.1 or 1.2 or more to improve reliability.
With respect to claim 18, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in an outermost portion in the first direction among the internal electrodes, is defined as tc2 (see Park FIG. 4, element tc2) and a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in a central portion in the first direction among the internal electrodes, is defined as tc1 (see Park FIG. 4, element tc1), a ratio tc2/tc1 is 0.9 or more and 1.0 or less (see Park paragraphs 110 and 111, noting a ratio of a thickness tc2 to a thickness tc1 may be 0.9 or more and 1.0 or less).
With respect to claim 19, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when a thickness of the first or second side margin portion in contact with an edge of the body is defined as tc3 (see Park FIG. 4, element tc3) and a thickness of the first or second side margin portion in contact with an end of an internal electrode in the third direction, disposed in a central portion in the first direction among the internal electrodes, is defined as tc1 (see Park FIG. 4, element tc1), a ratio tc3/tc1 is 0.9 or more and 1.0 or less (see Park paragraphs 119 and 120, noting a ratio of a thickness tc3 to a thickness tc1 may be 0.9 or more and 1.0 or less).
With respect to claim 20, the combined teachings of Lee, Park, Iguchi and Kaneko teach that when an average grain size of the dielectric layer in a central region of the first cover portion or the second cover portion is defined as G4, 1 < G4/GO< 1.3 is satisfied (see Kaneko paragraph 50, noting Dh’/Di is 1.1 or 1.2 or more which satisfied the claim limitation). It would clearly be well within the per view of a person having ordinary skill Dg/Di to be 1.1 or 1.2 or more to improve reliability.
Claim 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Park, Iguchi and Kaneko, as applied to claim 11 above, and further in view of An et al. (US20220270824).
With respect to claim 14, Lee, Park, Iguchi and Kaneko teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 11.
Lee, Park, Iguchi and Kaneko do not teach when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second cover portions is defined as G1, 1 < G1/G0 < 1.3 is satisfied.
An, on the other hand, teaches when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 2, element 111, paragraph 37, noting Gc is a central region of the capacitance formation portion), and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second cover portions is defined as G1 (see FIG. 2, element 120, paragraph 37, noting Gm is an outer region of the capacitance formation portion 120), 1 < G1/G0 < 1.3 is satisfied (see paragraph 37, noting a ratio of Gm/Gc may be less than 1.3).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and Kaneko to form the claimed invention in order to improve reliability of a multilayer ceramic electronic component (see An paragraph 60).
With respect to claim 15, Lee, Park, Iguchi and Kaneko teaches a multilayer electronic component (see Lee FIG. 1, element 100) of claim 11.
Lee, Park, Iguchi and Kaneko do not teach when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0, and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second side margin portions is defined as G2, 0.9 < G2/G0 < 1.3 is satisfied.
An, on the other hand, teaches when an average grain size of the dielectric layer in a central region of the capacitance forming portion is defined as G0 (see FIG. 2, element 111, paragraph 37, noting Gc is a central region of the capacitance formation portion), and an average grain size of the dielectric layer in a region in which the capacitance forming portion is adjacent to the first and second side margin portions is defined as G2 (see FIG. 2, element 120, paragraph 37, noting Gm is an outer region of the capacitance formation portion 120), 0.9 < G2/G0 < 1.3 is satisfied (see paragraph 37, noting a ratio of Gm/Gc may be less than 1.3).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lee, Park, Iguchi and Kaneko to form the claimed invention in order to improve reliability of a multilayer ceramic electronic component (see An paragraph 60).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESTHER N LIAN whose telephone number is (571)272-5726. The examiner can normally be reached Monday-Friday 8:00 - 5:00 ET.
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/ESTHER N LIAN/Examiner, Art Unit 2848
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2848