DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) -1, 12, 20; 2, 4, 7, 8, 13, 14, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. U.S. Pub. No. 2024/0192758 in view of Takagi U.S. Pub. No. 2025/0358547.
Re: claims 1 and 20 (which are rejected under the same rationale), Nomura teaches
1. A method comprising:... wherein the first data has a first bitwidth; (“The controller 18 acquires the effective data length of the layer, for each layer... In the convolutional computation processing, the effective data length corresponding to the layer that is a calculation target is acquired by the controller 18, and the effective data length is set in the power gate control unit 17. ”; Nomura, [0050], [0056])
The controller acquires the data length (first data has a first bitwidth) of the layer that includes the image.
determining that the first bitwidth is less than a predetermined bitwidth associated with the processor; (“the element data and the weight data have a constant length with a fixed data length of N bits, in which N is an integer of 2 or more, and in this example, an effective data length (an upper bit number) is set in advance with respect to the element data and the weight data for each layer... In a case where M is an integer of 2 or more, and the effective data length is M bits, “N≥M” is obtained, and the effective data length of the element data and the weight data is identical to or shorter than the original data length.”; Nomura, [0042])
The element data and weight data have an original fixed data length of N bits (predetermined bitwidth associated with the processor), where N is 2 or more. An effective data length M is set with respect to the element data and the weight data for each layer, where M is 2 or more. In this case the N≥M, where the effective data length is less than or equal to the original data length. In this case, the effective data length M is determined to be less than or equal to the original fixed data length N (predetermined bitwidth associated with the processor).
determining a first operating mode for the processor based on a difference between the first bitwidth and the predetermined bitwidth, wherein the first operating mode disables at least a subset of a plurality of bit registers within the processor; (“In Fig. 3, in the second storage circuit 22, a memory array is provided in which a plurality of non-volatile memory cells 31 are arrayed into the shape of a matrix, and the memory array is divided into a plurality of memory blocks MB. In this example, one memory block MB includes N memory cells 31 arranged in one row in a horizontal direction of the drawing, and each of the memory blocks MB retains one data piece of a maximum of N bits. The number of memory cells 31 configuring the memory block MB may be set in accordance with the maximum data length of data to be retained.”; Nomura, [0051], Fig. 3)
Fig. 3 illustrates a memory array, which includes plural memory cells (bit registers). The memory array is divided into memory blocks, where one memory block includes N memory cells, and where each memory block stores one data piece of a maximum of N bits. The number of memory cells is set according to the maximum data length to be retained.
(“In the convolutional computation processing, in a case where the effective data length is set from the controller, the power gate control unit 17 turns on the PG switches 33a corresponding to the upper M bits indicated by the effective data length of the memory block MB, and turns off the other PG switches 33a. Accordingly, the power supply to the memory cell 31 retaining bits other than the upper bits of the bit number used in the convolutional computation processing of the target layer is blocked to reduce the power consumption.”; Nomura, [0055])
When the effective data length is obtained, the power gate controller unit turns on the PG switches corresponding to the upper M bits indicated by the effective data length of the memory block and turns off the other PG switches (determining a first operating mode for the processor based on a difference between the first bitwidth and the predetermined bitwidth, wherein the first operating mode disables at least a subset of a plurality of bit registers within the processor).
(“In a case where the effective data length is set, the power gate control unit 17 turns on the PG switches 33 for the upper bits indicated by the set effective data length, and turns of the other PG switches 33. Accordingly, in each of the memory blocks MB of the second storage circuit 22, power is supplied to the memory cells 31 for the effective data length, and the power supply to the other memory cells 31 is blocked... the power consumption is reduced while enabling the read of the data portion of the effective data length of the element data and the weight data used in the computation.”; Nomura, [0057])
In each of the memory blocks, power is supplied to the memory cells for the effective data length and power supply to the other memory cells is blocked. Thus, it is determined that the processor will operate at a reduced power consumption level based on the effective data length being less than the original (predetermined) data length.
and determining, by the processor in the first operating mode, first output data based on the first data. (“As an example of the case of setting the original data length of the element data of the previous layer and the weight data of the convolutional filter to the previous layer to 8 bits (N=8) is illustrated in Fig. 5... as illustrated in Fig. 5(B), in a case where the element data of the next layer is calculated with the effective data length as 4 bits (M=4), power is supplied to the memory cells 31 of the upper 4 bits in each of the memory blocks MB of the second storage circuit 22 (ON), and the power supply to the memory cells 31 of the lower 4 bits is blocked (OFF). In this case, in the element data and the weight data, the upper 4 bits corresponding to the effective data length are read out from the second storage circuit 22, and are input to the computation circuit unit 16 as the element data and the weight data of 4 bits to be provided to the computation.”; Nomura, [0058], [0059])
Fig. 5B illustrates that effective data length of M=4 bits (first bitwidth) is less than the original data length of N=8 bits (predetermined data length), then the processor is determined to operate at a lower power state such that power is supplied to the upper 4 bits in each of the memory blocks and the power supply is off for the lower 4 bits. Then the upper 4 bits of this data corresponding to the effective data length are read out and input to the computation circuit for computation (determining, by the processor in the first operating mode, first output data based on the first data).
Nomura teaches ... receiving, at a processor, first data from a first sensor, (“The convolutional processing unit 12 corresponds to a neural network to which a plurality of layers are connected. Each of the layers includes one or a plurality of channels. The first layer is an input layer, and for example, is an image including each channel of RGB, and the like.”; Nomura, [0030])
Each layer of the convolutional processing unit includes an image (first data) with channels for each of RGB. Nomura is silent regarding the first data being received from a first sensor, however, Takagi teaches this limitation.
(“Each of the cameras 3 includes for example an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor and captures an image of a subject to obtain image data (captured image data) as digital data. In addition... each of the camera 3 also has a function of performing image processing (AI image processing), such as image recognition processing using an AI model, on the captured image.”; Takagi, [0202], Fig. 14)
Fig. 14 illustrates plural cameras, where each camera includes an image sensor (first sensor). Each camera also performs image processing on the captured image (receiving, at a processor, first data from a first sensor). Takagi is combined with Nomura such that the captured image of Takagi is input layer image of Nomura.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify device of Nomura by adding the feature of receiving, at a processor, first data from a first sensor, in order to generate analysis information of a subject based on processing result information obtained by AI image processing of each of the cameras, as taught by Takagi ([0204]).
Claim 12 is a device analogous to the method of claim 1, is similar in scope and is rejected under the same rationale. Claim 12 has additional limitations. Re: claim 12, Namura teaches
12. A device comprising:... one or more processors comprising a first processor configured to: (“The convolutional processing unit 12 corresponds to a neural network to which a plurality of layers are connected. Each of the layers includes one or a plurality of channels. The first layer is an input layer, and for example, is an image including each channel of RGB, and the like.”; Nomura, [0030], Fig. 1)
Fig. 1 illustrates that the device includes a convolutional processing unit (one or more processor comprising a first processor).
... determine, in the first operating mode, first output data based on the first data; and one or more memories configured to receive and store the first output data. (“As an example of the case of setting the original data length of the element data of the previous layer and the weight data of the convolutional filter to the previous layer to 8 bits (N=8) is illustrated in Fig. 5... as illustrated in Fig. 5(B), in a case where the element data of the next layer is calculated with the effective data length as 4 bits (M=4), power is supplied to the memory cells 31 of the upper 4 bits in each of the memory blocks MB of the second storage circuit 22 (ON), and the power supply to the memory cells 31 of the lower 4 bits is blocked (OFF). In this case, in the element data and the weight data, the upper 4 bits corresponding to the effective data length are read out from the second storage circuit 22, and are input to the computation circuit unit 16 as the element data and the weight data of 4 bits to be provided to the computation.”; Nomura, [0058], [0059], Figs. 1 and 5B)
Fig. 5B illustrates that effective data length of M=4 bits (first bitwidth) is less than the original data length of N=8 bits (predetermined data length), then the processor is determined to operate at a lower power state such that power is supplied to the upper 4 bits in each of the memory blocks and the power supply is off for the lower 4 bits. Then the upper 4 bits of this data corresponding to the effective data length are read out and input to the computation circuit for computation (determine, in the first operating mode, first output data based on the first data). Fig. 1 illustrates that the output of the computation circuit unit is stored in the first storage circuit (one or more memories configured to receive and store the first output data.
Namura is silent regarding one or more sensors comprising a first sensor, however, Takagi teaches
... one or more sensors comprising a first sensor; (“Each of the cameras 3 includes for example an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor and captures an image of a subject to obtain image data (captured image data) as digital data. In addition... each of the camera 3 also has a function of performing image processing (AI image processing), such as image recognition processing using an AI model, on the captured image.”; Takagi, [0202], Fig. 14)
Fig. 14 illustrates plural cameras, where each camera includes an image sensor (one or more sensors comprising a first sensor). Takagi is combined with Nomura such that the captured image of Takagi is input layer image of Nomura. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify device of Nomura by adding the feature of one or more sensors comprising a first sensor, in order to generate analysis information of a subject based on processing result information obtained by AI image processing of each of the cameras, as taught by Takagi ([0204]).
Re: claims 2 and 13 (which are rejected under the same rationale), Nomura and Takagi teach
2. The method of claim 1, wherein the subset of the bit registers are disabled to zero out values for bits in positions greater than the first bitwidth. (“... as illustrated in Fig. 5(B), in a case where the element data of the next layer is calculated with the effective data length as 4 bits (M=4), power is supplied to the memory cells 31 of the upper 4 bits in each of the memory blocks MB of the second storage circuit 22 (ON), and the power supply to the memory cells 31 of the lower 4 bits is blocked (OFF).”; Nomura, [0059])
Fig. 5B illustrates that the original data length is N=8 bits (predetermined bitwidth) and the effective data length is M=4 bits (first bitwidth). In this case power is supplied to the memory cells of the upper 4 bits in each of the memory blocks and the power is not supplied (disabled to zero out values for bits in positions greater than the first bitwidth) to the memory cells (subset of the bit registers) of the lower 4 bits.
Re: claims 4 and 15 (which are rejected under the same rationale), Nomura and Takagi teach
4. The method of claim 1, wherein the predetermined bitwidth is a maximum supported bitwidth of the processor. (“In Fig. 3, in the second storage circuit 22, a memory array is provided in which a plurality of non-volatile memory cells 31 are arrayed into the shape of a matrix, and the memory array is divided into a plurality of memory blocks MB. In this example, one memory block MB includes N memory cells 31 arranged in one row in a horizontal direction of the drawing, and each of the memory block is MB retains one data piece of a maximum of N bits. The number of memory cells 31 configuring the memory block MB may be set in accordance with the maximum data length to be retained.”; Nomura, [0051], Figs. 1 and 3 )
Fig. 1 illustrates that the convolutional processing unit 12 includes a second storage circuit 22. Fig. 3 illustrates that the second storage unit is a memory array of memory cells divided into memory blocks, where each memory block stores data of a maximum of N bits (the predetermined bitwidth is a maximum supported bitwidth of the processor).
Re: claims 7 and 18 (which are rejected under the same rationale), Nomura and Takagi teach
7. The method of claim 1, wherein the difference between the first bitwidth and the predetermined bitwidth is determined by a first component of the processor and is signaled to other components of the processor to disable the subset of bit registers. (“... as illustrated in Fig. 5(B), in a case where the element data of the next layer is calculated with the effective data length as 4 bits (M=4), power is supplied to the memory cells 31 of the upper 4 bits in each of the memory blocks MB of the second storage circuit 22 (ON), and the power supply to the memory cells 31 of the lower 4 bits is blocked (OFF).”; Nomura, [0059])
Fig. 5B illustrates that the original data length is N=8 bits (predetermined bitwidth) and the effective data length is M=4 bits (first bitwidth). In this case power is supplied to the memory cells of the upper 4 bits in each of the memory blocks and the power is not supplied (disable) to the memory cells (bit registers) of the lower 4 bits (the difference between the first bitwidth and the predetermined bitwidth is determined by a first component of the processor and is signaled to other components of the processor to disable the subset of bit registers).
Re: claim 8, Nomura and Takagi teach
8. The method of claim 1, further comprising: receiving, at the processor, second data from a second sensor, wherein the second data has a second bitwidth different from the first bitwidth; (“In the convolutional computation processing, the effective data length corresponding to the layer that is a calculation target is acquired by the controller 18, and the effective data length is set in the power gate control unit 17.”; Nomura, [0056])
The layer (second data from a second sensor) is obtained by the controller (receiving, at the processor). The layer has an effective data length (second data has a second bitwidth different from the first bitwidth).
(“... as illustrated in Fig. 5(B), in a case where the element data of the next layer is calculated with the effective data length as 4 bits (M=4), power is supplied to the memory cells 31 of the upper 4 bits in each of the memory blocks MB of the second storage circuit 22 (ON), and the power supply to the memory cells 31 of the lower 4 bits is blocked (OFF).”; Nomura, [0059])
Fig. 5B illustrates that the original data length is N=8 bits and the effective data length is M=4 bits. In this case power is supplied to the memory cells of the upper 4 bits in each of the memory blocks and the power is not supplied to the memory cells of the lower 4 bits. Thus, the effective data length of M=4 (first bitwidth) is different from Fig. 5A, where the effective bit width is M=8 (second bitwidth different from the first bitwidth).
determining that the second bitwidth is equal to the predetermined bitwidth associated with the processor; determining a second operating mode for the processor based on the determination that the second bitwidth is equal to the predetermined bitwidth; (“As an example of the case of setting the original data length of the element data of the previous layer and the weight data of the convolutional filter applied to the previous layer to 8 bits (N=8) is illustrated in Fig. 5, in a case where the element data of the next layer is calculated by the convolutional computation processing with the effective data length as 8 bits (M=8), as illustrated in Fig. 5(A), power is supplied to all of the memory cells 31 for the 8 bits in each of the memory blocks MB of the second storage circuit 22 (ON).”; Nomura, [0058], [0059], Fig. 5A)
Fig. 5A illustrates that the original data length is N=8 bits (predetermined bitwidth) and the effective data length is M=8 bits (second bitwidth is equal to the predetermined bitwidth associated with the processor). The operating mode is determined, based on N=M=8 bits, to be that power is suppled to all of the memory cells for the 8 bits of the memory blocks of the second storage circuit (determining a second operating mode for the processor based on the determination that the second bitwidth is equal to the predetermined bitwidth).
and determining, by the processor in the second operating mode, second output data based on the second data. (“In this case, the element data of 8 bits and the weight data of 8 bits are read out from the second storage circuit 22, and are sent to the computation circuit unit 16.”; Nomura, [0058])
The 8 bits are read out from the second storage circuit and sent to the computation circuit unit for output (determining, by the processor in the second operating mode, second output data based on the second data).
Claim(s) 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura and Takagi as applied to claims 1 and 12 above, and further in view of Garg et al. U.S. Pub. No. 2008/0155135.
Re: claims 3 and 14 (which are rejected under the same rationale), Nomura and Takagi are silent regarding the subset of the bit registers are disabled using clock gating, however, Garg teaches
3. The method of claim 1, wherein the subset of the bit registers are disabled using clock gating. (“Applicant has appreciated that by providing a clock gate structure, clocks synchronizing transfers to and from the buffers may be gated off when the buffers are not in use, thus conserving the power needed to drive the clock signals when the clock signals are unnecessary.”; Garg, [0027])
A clock gate structure is provided such that when buffers (bit registers) are gated off when they are not in use (the subset of the bit registers are disabled using clock gating). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the device of Nomura by adding the feature of the subset of the bit registers are disabled using clock gating, in order to conserve the power needed to drive the clock signals when the clock signals are unnecessary, as taught by Garg ([0027]).
Claim(s) 5 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura and Takagi as applied to claims 1 and 12 above, and further in view of Ding et al. U.S. Pub. No. 2025/0103295.
Re: claims 5 and 16 (which are rejected under the same rationale), Nomura and Takagi are silent regarding determining aligned first data by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data, however, Ding teaches
5. The method of claim 1, further comprising determining aligned first data by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data. (“For example, in autonomous driving scenarios, if the multiply-accumulate array is used for convolution operations on an image feature, statistics about a signal logging probability of each bit may be collected based on image features that correspond to a batch of sample images and need to be calculated by using the multiply-accumulate array, which may be used for dividing the second calculation arrays of the multiply-accumulate array.”; Ding, [0028])
A multiply-accumulate array is used for convolution operations on an image feature (first data).
(“For example, a least significant bit of the encoded data is 1, and the encoded data is multiplied with weight data 10110111. Thus, a calculation result 10110111 corresponding to the least significant bit is obtained. According to a multiplication operation rule, as shown in Fig. 1, calculation results of different bits of the encoded data need to be aligned in a staggering way. For example, a second least significant bit of the encoded data is also 1, and the calculation result 10110111 obtained is aligned with the calculation result 10110111 corresponding to the least significant bit in a staggering way. This is equivalent to that one 0 is added after the least significant bit of the calculation result of the second least significant bit to obtain 101101110, and a least significant bit of 10110110 is aligned with a least significant bit of the calculation result 10110111 of the least significant bit.”; Ding, [0034])
For example, a least significant bit (LSB) of the encoded data is 1 and it is multiplied with weight data, where the calculation result corresponding to the LSB is obtained. A second LSB least significant bit of the encoded data is also 1, and the calculation result obtained is aligned with the calculation result corresponding to the LSB (determining aligned first data by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the device of Nomura by adding the feature of determining aligned first data by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data, in order to perform in-depth power consumption optimization on the multiply-accumulate array, as taught by Ding ([0028]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura and Takagi as applied to claim 8 above, and further in view of Wexler et al. U.S. Pub. No. 2014/0204245.
Re: claim 9, Nomura and Takagi are silent regarding the second data is received as a consecutive image frame after the first data within a stream of image frames received by the processor, however, Wexler teaches
9. The method of claim 8, wherein the second data is received as a consecutive image frame after the first data within a stream of image frames received by the processor. (“Image sensor 220 (which may include image sensor 220a and/or 220b) may capture at least one image with one or more capturing parameters set to a specified value... the image or plurality of images may capture a portion of an environment of a user as image data (e.g., images, videos, etc.). Image sensor 220 may capture the image data, which may be transmitted to other components of apparatus 110 for further processing, such as processing via identification module 610.”; Wexler, [0087], Fig. 5B)
The image sensor captures images, such as video images (second data is received as a consecutive image frame after the first data within a stream of image frames) and transmits these images to a processor for further processing (received by the processor. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the device of Nomura by adding the feature of the second data is received as a consecutive image frame after the first data within a stream of image frames received by the processor, in order to capture and store image information in a manner that preserves battery-life and storage space, as taught by Wexler ([0009]).
Claim(s) 10, 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura and Takagi as applied to claims 1, 8 and 12 above, and further in view of Jeong et al. U.S. Pub. No. 2022/0053150.
Re: claim 10, Nomura and Takagi are silent regarding storing, within the processor, (i) an indicator of the first bitwidth in association with an identifier of the first sensor and (ii) an indicator of the second bitwidth in association with an identifier of the second sensor, however, Jeong teaches
10. The method of claim 8, further comprising storing, within the processor, (i) an indicator of the first bitwidth in association with an identifier of the first sensor (“... the bit depth of the pieces of pixel data of the first camera module 100a (e.g., bit depth of pieces of pixel data included in the image data output by the first camera module 100a to the application processor 200) is 10 or fewer bits”; Jeong, [0056])
The bit depth, of 10 bits or less, is indicated (indicator of the first bitwidth) by the pixel data included in the image data output by the first camera module (in association with n identifier of the first sensor) and stored in the application processor (storing within the processor).
and (ii) an indicator of the second bitwidth in association with an identifier of the second sensor. (“... the image processor 210 may be configured to control the second camera module 100b according to the first still image mode to cause the second camera module to deliver pieces... of pixel data... corresponding to one or more second images captured by the second camera module 100b to the image processor 210 at a first output speed... and a first bit depth (e.g., 10 to 14 bits).”; Jeong, [0055])
The bit depth, of 10 to 14 bits (indicator of the second bitwidth), is indicated by the second images captured by the second camera module (in association with an identifier of the second sensor) and stored in the image processor (storing, within the processor). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the device of Nomura by adding the feature of storing, within the processor, (i) an indicator of the first bitwidth in association with an identifier of the first sensor and (ii) an indicator of the second bitwidth in association with an identifier of the second sensor, in order to adjustably control an output of a camera module (e.g., at least one of the output speed or the bit depth associated with the output) according to a selected mode, as taught by Jeong ([0054]).
Re: claims 11 and 19 (which are rejected under the same rationale), Nomura and Takagi teach
11. The method of claim 1, wherein the first data is image data, wherein the first sensor is an image sensor, (“Each of the cameras 3 includes, for example, an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor, and captures an image of a subject to obtain image data (captured image data) as digital data.”; Takagi, [0202], Fig. 14)
Fig. 14 illustrates plural cameras, where each camera includes an image sensor (first sensor is an image sensor) and where each camera captures image data (first data is image data). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify device of Nomura by adding the feature of the first data is image data, wherein the first sensor is an image sensor, in order to generate analysis information of a subject based on processing result information obtained by AI image processing of each of the cameras, as taught by Takagi ([0204]).
Nomura and Takagi are silent regarding the first bitwidth is a per-pixel bitwidth of the first data, however, Jeong teaches this limitation.
and wherein the first bitwidth is a per-pixel bitwidth of the first data. (“Each mode, of the plurality of still image modes and the plurality of video modes, may be configured to control an output of at least the second camera module 100b under a condition in which at least one of an output speed... at which pieces of pixel data are converted into a digital signal at the second camera module 100b and/or at which image data is transmitted by the second camera module 100b or a bit depth (e.g., a quantity of bits used to indicate a color of a pixel of a captured image) of image data output (e.g., transmitted, generated, etc.) by the second camera module 100b is different.”; Jeong, [0054])
The bit depth (first bitwidth) of the captured image (first data) is a quantity of bits used to indicate a color of a pixel of a captured image (is a per-pixel bitwidth of the first data). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the device of claim 1 by adding the feature of the first bitwidth is a per-pixel bitwidth of the first data, in order to adjustably control an output of a camera module (e.g., at least one of the output speed or the bit depth associated with the output) according to a selected mode, as taught by Jeong ([0054]).
Allowable Subject Matter
Claims 6 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art teaches or suggests:
From claims 6 and 17 – “wherein one or more software interface (SWI) components of the processor are configured to use LSB-aligned data.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618