DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 01/08/2026.
Drawings
The drawings are objected to because the empty boxes (e.g. 305 and 307) in figure 3 should contain symbols or text indicating their functionality (example: a voltage regulator supply 305 and a 1.5V voltage regulator 307). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US 10,651,843), hereinafter Kinzer, in view of Horiguchi et al. (US 2018/0115310), hereinafter Horiguchi.
Regarding claim 1, Kinzer discloses (see figures 1-11) a cycloconverter (figure 7, part cycloconverter AC-AC generated by 430, 440, 450 and 460) configured for use with a power converter (figure 7, part 400) (columns 11 and 12; lines 63-67 and 1-3; a power inverter circuit 400) comprising: a bidirectional switch (figure 7, part 430 or 440) comprising a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part Q5/Q6 or Q9/Q10) (claim 3; the first and second bidirectional switch circuits comprises a single substrate, wherein the first and second transistors and the at least one transistor driver of each of the first and second bidirectional switch circuits comprise GaN-based transistors); and a Gate driver (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) coupled to a gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part gate of Q5/Q6 or Q9/Q10) and configured to provide (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) at least one of independent turn-on and turn-off outputs (figure 7, part turn-on and turn-off outputs from gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) for implementing asymmetrical Gate drive characteristics (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) (columns 12 and 13; lines 57-67 and 1-28; Input signal IQ5/9 is applied to transistor drivers G1 and G3. In addition, input signal IQ6/10 is respectively applied to transistor drivers G2 and G4. Bidirectional switches 430 and 440 are turned on and off in response to input signals IQ5/9 and IQ6/10), a voltage regulated supply (figure 7, part a voltage regulated supply from 470 and 475 to G1/G2 or a voltage regulated supply from 480 and 485 to G3/G4) (figure 5, part through pull-up FET 12444 [at G1/G2 or G3/G4]) (claim 7; Zener diode is configured to regulate a voltage to which the capacitor is charged) to determine a gate turn-on voltage (figure 7, part gate turn-on voltage of Q5/Q6 or Q9/Q10) (columns 10 and 11; lines 41-67 and 1-5; turning off pull-down device FET 12442 and FET 12432, respectively allowing the output and the gate of pull-up device FET 12444 to go High. In addition, FET 12422 turns off, allowing the voltage at its drain to go High. This causes the capacitor 12425 to inject charge onto the gate of pull-up device FET 12444 through resistor 12436, thereby causing the gate of pull-up device FET 12444 to go above Vdd (e.g. approximately 2*Vdd−Vth). In response to its gate voltage, pull-up device FET 12444 drives the output to Vdd), or a gate turn-off voltage supply (figure 7, part gate turn-off voltage of Q5/Q6 or Q9/Q10) that can sink and source current (figure 5, part through pull-down FET 12442 [at G1/G2 or G3/G4]) (columns 10 and 11; lines 41-67 and 1-5; turns on pull-down device FET 12442, causing output to go Low. Also, the output of the first inverter 12410 being High causes FET 12432 to pull the gate of pull-up device FET 12444 low, which turns off FET 12444), wherein during operation, a Gate drive logic signal at an output Gate G (figure 5, part Gate drive logic signal Vin) drives an upper drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 5, part 12444) and a lower drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 5, part 12442) such that the upper drive transistor (figure 5, part 12444) is driven by the Gate drive logic signal at the output of gate G (figure 5, part Gate drive logic signal Vin) and the lower drive transistor (figure 5, part 12442) is driven (figure 5, part through 12410) so that the upper drive transistor is on (figure 5, part 12444; turn-on) while the lower drive transistor is off and vice versa (figure 5, part 12442; turn-off) (columns 10 and 11; lines 41-67 and 1-5; In response to Vin being Low, the output of the first inverter 12410 is High, which turns on pull-down device FET 12442, causing output to go Low. Also, the output of the first inverter 12410 being High causes FET 12432 to pull the gate of pull-up device FET 12444 low, which turns off FET 12444… In response to Vin transitioning High, the output of the first inverter 12410 transitions Low, turning off pull-down device FET 12442 and FET 12432, respectively allowing the output and the gate of pull-up device FET 12444 to go High. In addition, FET 12422 turns off, allowing the voltage at its drain to go High. This causes the capacitor 12425 to inject charge onto the gate of pull-up device FET 12444 through resistor 12436, thereby causing the gate of pull-up device FET 12444 to go above Vdd (e.g. approximately 2*Vdd−Vth). In response to its gate voltage, pull-up device FET 12444 drives the output to Vdd).
Kinzer does not expressly disclose the upper drive transistor is driven directly by the Gate drive logic signal at the output of gate G and the lower drive transistor is driven via a logic inverter so that the upper drive transistor is on while the lower drive transistor is off and vice versa.
Horiguchi teaches (see figures 1-22) during operation, a Gate drive logic signal at an output Gate G (figure 5, part Sg) drives an upper drive transistor (figure 5, part 21) and a lower drive transistor (figure 5, part 22) (paragraph [0042]; Voltage driver 3 includes semiconductor switches 21 and 22… each semiconductor switch to be used is a semiconductor switching element such as a bipolar transistor or a MOSFET) such that the upper drive transistor (figure 5, part 21) is driven directly by the Gate drive logic signal at the output of gate G (figure 5, part Sg) and the lower drive transistor (figure 5, part 22) is driven via a logic inverter (figure 5, part 23) so that the upper drive transistor is on (figure 5, part 21; turn-on) while the lower drive transistor is off and vice versa (figure 5, part 22; turn-off) (paragraphs [0038]-[0045]; Semiconductor switch 21 is turned on and off in response to control signal Sg. On the other hand, semiconductor switch 22 is turned on and off in response to the output from inverter 23 to which control signal Sg is input. In other words, semiconductor switches 21 and 22 are turned on and off complementarily in response to control signal Sg).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate driver of Kinzer with the gate driver features as taught by Horiguchi and obtain a cycloconverter configured for use with a power converter, comprising: a bidirectional switch comprising a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors; and a Gate driver coupled to a gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors and configured to provide at least one of independent turn- on and turn-off outputs for implementing asymmetrical Gate drive characteristics, a voltage regulated supply to determine a gate turn-on voltage, or a gate turn-off voltage supply that can sink and source current, wherein during operation, a Gate drive logic signal at an output Gate G drives an upper drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors and a lower drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors such that the upper drive transistor is driven directly by the Gate drive logic signal at the output of gate G and the lower drive transistor is driven via a logic inverter so that the upper drive transistor is on while the lower drive transistor is off and vice versa, because it provides more efficient driver with simpler and more cheap circuit (paragraph [0010]).
Regarding claim 2, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part Q5/Q6 or Q9/Q10) are one of a Cascode GaN HEMT device, a gate injection transistor (GIT) GaN eHEMT device, or a Schottky Gate GaN eHEMT device (figure 7, part Q5/Q6 or Q9/Q10) (claim 3; the first and second bidirectional switch circuits comprises a single substrate, wherein the first and second transistors and the at least one transistor driver of each of the first and second bidirectional switch circuits comprise GaN-based transistors).
Regarding claim 3, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the Gate driver (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) and respective turn-on and turn-off outputs of the Gate driver (figure 7, part turn-on and turn-off outputs from gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10). However, Kinzer does not expressly disclose Resistors R1 and R2 connected to respective turn-on and turn-off outputs of the Gate driver.
Horiguchi teaches (see figures 1-22) the Gate driver (figure 1, part gate driver at 51) comprises Resistors R1 (figure 1, part 2a) and R2 (figure 1, part 2B) connected to respective turn-on (figure 1, part turn-on output from 2a) and turn-off outputs (figure 1, part turn-off output from 2b) of the Gate driver (figure 1, part gate driver at 51).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate driver of Kinzer with the gate driver features as taught by Horiguchi and obtain the Gate driver comprises Resistors R1 and R2 connected to respective turn-on and turn-off outputs of the Gate driver, because it provides more efficient driver with simpler and more cheap circuit (paragraph [0010]).
Regarding claim 6, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the Gate driver is on a single PCB (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) (column 14; lines 27-59; it may comprise an organic printed circuit board, a ceramic circuit or another material).
Regarding claim 8, Kinzer discloses (see figures 1-11) a power conversion system (figure 7), comprising: a converter (figure 7, part 400); a DC component (figure 7, part DC at input of 410) coupled to a DC side of the converter (figure 7, part DC side of 400); a plurality of switches (figure 7, parts Q1-Q4) coupled to a primary winding of a transformer (figure 7, part primary winding of 420); and a cycloconverter (figure 7, part cycloconverter AC-AC generated by 430, 440, 450 and 460) coupled to a secondary winding of the transformer (figure 7, part secondary winding of 420) (columns 11 and 12; lines 63-67 and 1-3; a power inverter circuit 400) and comprising: a bidirectional switch (figure 7, part 430 or 440) comprising a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part Q5/Q6 or Q9/Q10) (claim 3; the first and second bidirectional switch circuits comprises a single substrate, wherein the first and second transistors and the at least one transistor driver of each of the first and second bidirectional switch circuits comprise GaN-based transistors); and a Gate driver (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) coupled to a gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part gate of Q5/Q6 or Q9/Q10) and configured to provide (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) at least one of independent turn-on and turn-off outputs (figure 7, part turn-on and turn-off outputs from gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) for implementing asymmetrical Gate drive characteristics (figure 7, part gate driver at 430 or 440 connected to gate of Q5/Q6 or Q9/Q10) (columns 12 and 13; lines 57-67 and 1-28; Input signal IQ5/9 is applied to transistor drivers G1 and G3. In addition, input signal IQ6/10 is respectively applied to transistor drivers G2 and G4. Bidirectional switches 430 and 440 are turned on and off in response to input signals IQ5/9 and IQ6/10), a voltage regulated supply (figure 7, part a voltage regulated supply from 470 and 475 to G1/G2 or a voltage regulated supply from 480 and 485 to G3/G4) (figure 5, part through pull-up FET 12444 [at G1/G2 or G3/G4]) (claim 7; Zener diode is configured to regulate a voltage to which the capacitor is charged) to determine a gate turn-on voltage (figure 7, part gate turn-on voltage of Q5/Q6 or Q9/Q10) (columns 10 and 11; lines 41-67 and 1-5; turning off pull-down device FET 12442 and FET 12432, respectively allowing the output and the gate of pull-up device FET 12444 to go High. In addition, FET 12422 turns off, allowing the voltage at its drain to go High. This causes the capacitor 12425 to inject charge onto the gate of pull-up device FET 12444 through resistor 12436, thereby causing the gate of pull-up device FET 12444 to go above Vdd (e.g. approximately 2*Vdd−Vth). In response to its gate voltage, pull-up device FET 12444 drives the output to Vdd), or a gate turn-off voltage supply (figure 7, part gate turn-off voltage of Q5/Q6 or Q9/Q10) that can sink and source current (figure 5, part through pull-down FET 12442 [at G1/G2 or G3/G4]) (columns 10 and 11; lines 41-67 and 1-5; turns on pull-down device FET 12442, causing output to go Low. Also, the output of the first inverter 12410 being High causes FET 12432 to pull the gate of pull-up device FET 12444 low, which turns off FET 12444), wherein during operation, a Gate drive logic signal at an output Gate G (figure 5, part Gate drive logic signal Vin) drives an upper drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 5, part 12444) and a lower drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 5, part 12442) such that the upper drive transistor (figure 5, part 12444) is driven by the Gate drive logic signal at the output of gate G (figure 5, part Gate drive logic signal Vin) and the lower drive transistor (figure 5, part 12442) is driven (figure 5, part through 12410) so that the upper drive transistor is on (figure 5, part 12444; turn-on) while the lower drive transistor is off and vice versa (figure 5, part 12442; turn-off) (columns 10 and 11; lines 41-67 and 1-5; In response to Vin being Low, the output of the first inverter 12410 is High, which turns on pull-down device FET 12442, causing output to go Low. Also, the output of the first inverter 12410 being High causes FET 12432 to pull the gate of pull-up device FET 12444 low, which turns off FET 12444… In response to Vin transitioning High, the output of the first inverter 12410 transitions Low, turning off pull-down device FET 12442 and FET 12432, respectively allowing the output and the gate of pull-up device FET 12444 to go High. In addition, FET 12422 turns off, allowing the voltage at its drain to go High. This causes the capacitor 12425 to inject charge onto the gate of pull-up device FET 12444 through resistor 12436, thereby causing the gate of pull-up device FET 12444 to go above Vdd (e.g. approximately 2*Vdd−Vth). In response to its gate voltage, pull-up device FET 12444 drives the output to Vdd).
Kinzer does not expressly disclose the upper drive transistor is driven directly by the Gate drive logic signal at the output of gate G and the lower drive transistor is driven via a logic inverter so that the upper drive transistor is on while the lower drive transistor is off and vice versa.
Horiguchi teaches (see figures 1-22) during operation, a Gate drive logic signal at an output Gate G (figure 5, part Sg) drives an upper drive transistor (figure 5, part 21) and a lower drive transistor (figure 5, part 22) (paragraph [0042]; Voltage driver 3 includes semiconductor switches 21 and 22… each semiconductor switch to be used is a semiconductor switching element such as a bipolar transistor or a MOSFET) such that the upper drive transistor (figure 5, part 21) is driven directly by the Gate drive logic signal at the output of gate G (figure 5, part Sg) and the lower drive transistor (figure 5, part 22) is driven via a logic inverter (figure 5, part 23) so that the upper drive transistor is on (figure 5, part 21; turn-on) while the lower drive transistor is off and vice versa (figure 5, part 22; turn-off) (paragraphs [0038]-[0045]; Semiconductor switch 21 is turned on and off in response to control signal Sg. On the other hand, semiconductor switch 22 is turned on and off in response to the output from inverter 23 to which control signal Sg is input. In other words, semiconductor switches 21 and 22 are turned on and off complementarily in response to control signal Sg).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate driver of Kinzer with the gate driver features as taught by Horiguchi and obtain a power conversion system, comprising: a converter; a DC component coupled to a DC side of the converter; a plurality of switches coupled to a primary winding of a transformer; and a cycloconverter coupled to a secondary winding of the transformer and comprising: a bidirectional switch comprising a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors; and a Gate driver coupled to a gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors and configured to provide at least one of independent turn- on and turn-off outputs for implementing asymmetrical Gate drive characteristics, a voltage regulated supply to determine a gate turn-on voltage, or a gate turn-off voltage supply that can sink and source current, wherein during operation, a Gate drive logic signal at an output Gate G drives an upper drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors and a lower drive transistor of the Gallium-Nitride (GaN) High Electron Mobility Transistors such that the upper drive transistor is driven directly by the Gate drive logic signal at the output of gate G and the lower drive transistor is driven via a logic inverter so that the upper drive transistor is on while the lower drive transistor is off and vice versa, because it provides more efficient driver with more simpler and cheap circuit (paragraph [0010]).
Regarding claim 9, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 10, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 13, claim 6 has the same limitations, based on this is rejected for the same reasons.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US 10,651,843), hereinafter Kinzer, in view of Horiguchi et al. (US 2018/0115310), hereinafter Horiguchi, and further in view of Qu et al. (US20240178831), hereinafter Qu.
Regarding claim 4, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the voltage regulated supply (figure 7, part a voltage regulated supply from 470 and 475 to G1/G2 or a voltage regulated supply from 480 and 485 to G3/G4) (claim 7; Zener diode is configured to regulate a voltage to which the capacitor is charged) to determine the gate turn-on voltage (figure 7, part gate turn-on voltage of Q5/Q6 or Q9/Q10) (figure 5, part through pull-up FET 12444 [at G1/G2 or G3/G4]) (columns 10 and 11; lines 41-67 and 1-5; turning off pull-down device FET 12442 and FET 12432, respectively allowing the output and the gate of pull-up device FET 12444 to go High. In addition, FET 12422 turns off, allowing the voltage at its drain to go High. This causes the capacitor 12425 to inject charge onto the gate of pull-up device FET 12444 through resistor 12436, thereby causing the gate of pull-up device FET 12444 to go above Vdd (e.g. approximately 2*Vdd−Vth). In response to its gate voltage, pull-up device FET 12444 drives the output to Vdd). However, Kinzer does not expressly disclose the voltage regulated supply to determine the gate turn-on voltage is adjustable/programmable.
Qu teaches (see figures 1-9) the voltage regulated supply (figure 7, part voltage regulated supply PVcc from voltage regulator to gate driving buffers) to determine the gate turn-on voltage (figure 7, part gate turn-on voltage for VG) is adjustable/programmable (figure 7, part through voltage regulator that adjust PVcc based on Vx and Vref).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate driver of Kinzer with the gate driver features as taught by Qu and obtain the voltage regulated supply to determine the gate turn-on voltage is adjustable/programmable, because it improves power efficiency, enhanced system reliability, and simplified hardware implementation (paragraph [0019]).
Regarding claim 11, claim 4 has the same limitations, based on this is rejected for the same reasons.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US 10,651,843), hereinafter Kinzer, in view of Horiguchi et al. (US 2018/0115310), hereinafter Horiguchi, and further in view of Illegems et al. (US 7,332,935), Illegems.
Regarding claim 5, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the gate turn-off voltage supply (figure 7, part gate turn-off voltage of Q5/Q6 or Q9/Q10) that can sink and source current is a Zener diode (figure 7, part 470 or 480) (figure 5, part through pull-down FET 12442 [at G1/G2 or G3/G4]) (columns 10 and 11; lines 41-67 and 1-5; turns on pull-down device FET 12442, causing output to go Low. Also, the output of the first inverter 12410 being High causes FET 12432 to pull the gate of pull-up device FET 12444 low, which turns off FET 12444). However, Kinzer does not expressly disclose voltage regulator.
Illegems teaches (see figures 1-5) the gate turn-off voltage supply (figure 4, part gate turn-off voltage supply at 260 from 225, 350 and 290) that can sink and source current (figure 4, part through 225, 350 and 290) is voltage regulator (figure 4, part voltage regulator 350) (column 5; lines 9-57; Voltage control circuit 350 may include an amplifier 355, a reference voltage source 358 (VL--REF), and a PMOS transistor 352 connected between sink current mirror 290, NMOS transistor 225, and bias current source 365… sink voltage control circuit 350 may implement a control loop to drive the drain terminal of NMOS transistor 225 to the desired sink voltage VN. Sink input terminal 220 may receive the sink control signal. If the received sink control signal is asserted, NMOS transistor 225 is turned on and driver circuit 150 enters a sink mode of operation).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate driver of Kinzer with the gate driver features as taught by Illegems and obtain the gate turn-off voltage supply that can sink and source current is a Zener diode and voltage regulator, respectively, because it provides more efficient gate driver with more accurate control the output current and output voltage (column 1; lines 7-18).
Regarding claim 12, claim 5 has the same limitations, based on this is rejected for the same reasons.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US 10,651,843), hereinafter Kinzer, in view of Horiguchi et al. (US 2018/0115310), hereinafter Horiguchi, and further in view of Udrea et al. (US 2020/0287536), Udrea.
Regarding claim 7, Kinzer and Horiguchi teach everything claimed as applied above (see claim 1). Further, Kinzer discloses (see figures 1-11) the gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors (figure 7, part gate of Q5/Q6 or Q9/Q10) has a threshold voltage, a drive voltage, and a maximum voltage (figure 7, part threshold voltage, a drive voltage, and a maximum voltage of gate of Q5/Q6 or Q9/Q10) (claim 3; the first and second bidirectional switch circuits comprises a single substrate, wherein the first and second transistors and the at least one transistor driver of each of the first and second bidirectional switch circuits comprise GaN-based transistors). However, Kinzer does not expressly disclose a threshold voltage of about 0.7V to about 4V, a drive voltage of about 1.2V to about 12V, and a maximum voltage of about 16V to about 18V.
Udrea teaches (see figures 1-19) the gate of Gallium-Nitride (GaN) High Electron Mobility Transistor (figure 11, part gate of 140) (paragraphs [0121]-[0122]; the pGaN HEMT 140) has a threshold voltage of about 0.7V to about 4V, a drive voltage of about 1.2V to about 12V (paragraph [0008]; A typical pGaN gate device has a threshold voltage of ˜1.5-2V and gate turn-on bias voltage of ˜8V).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the gate of each of the pair of (GaN) High Electron Mobility Transistors of Kinzer with the gate features as taught by Udrea, because it provides more efficient switching control.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to design the gate of each of the pair of Gallium-Nitride (GaN) High Electron Mobility Transistors of the combination of Kinzer, Horiguchi and Udrea with a threshold voltage of about 0.7V to about 4V, a drive voltage of about 1.2V to about 12V, and a maximum voltage of about 16V to about 18V, in order to obtain more accurate and efficient switching control for the gate driver with the design requirements. Additional, the invention would perform equally well with the gate driver of the combination of Kinzer and Udrea. Furthermore, In re Aller, 105 USPQ 233 (MPEP 2144.05 (II)) discloses discovering the optimum or workable ranges involves only routine skill in the art.
Regarding claim 14, claim 7 has the same limitations, based on this is rejected for the same reasons.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838