DETAILED ACTION
This office action is in response to the application filed on March 13, 2024.
Claims 1-15 are pending and have been examined. Claims 1-15 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
According to the USPTO guidelines, a claim is directed to non-statutory subject matter if:
Step 1: The claim does not fall within one of the four statutory categories of invention (process, machine, manufacture, or composition of matter) – see MPEP 2106.03, or,
Step 2: The claim recites a judicial exception, e.g. an abstract idea, without reciting additional elements that amount to significantly more than the judicial exception, as determined using the following analysis – see MPEP 2106.04:
Step 2A, Prong 1: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Step 2A, Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? - see MPEP 2106.05
Claims 11-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter in Step 1 because independent Claim 11 and dependent Claims 12-15 are directed to one or more “computer storage media” encoded with instructions to perform a set of operations, but the specification does not provide a definition limiting the claimed “computer storage media” to a non-transitory computer-readable storage medium. Instead, Paragraph 0051 in the specification expressly recites “alternatively or in addition, the carrier can be an artificially-generated propagated signal”. Under 35 U.S.C. 101, a propagated signal is not considered a process, machine, manufacture, or composition of matter. See MPEP 2106.03.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e. changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, and 11-14 are rejected under 35 U.S.C. 102 as being unpatentable over Gupte et al., (US Patent Application Number US20220035684A1 filed on May 26, 2021, hereinafter “Gupte”).
With respect to Claims 1, 6, and 11:
Gupte teaches:
“A method comprising:
retrieving multimedia data using a multimedia hardware accelerator of a first compute cluster of a system on a chip, (Paragraph 0055 recites a deep learning application that takes video as an input (retrieving multimedia data). Paragraph 0054 recites the application existing within a hardware accelerator, where a load balancer can distribute work to one or more VICs (Vision Image Compositors), one or more DPUs, and one or more GPUs to perform various operations of the application (using a multimedia hardware accelerator). Paragraph 0369 recites the system including one or more processors and one or more graphics processors (of a first compute cluster) incorporated within a system-on-a-chip (SOC) integrated circuit.)
wherein the first compute cluster includes (i) the multimedia hardware accelerator and (ii) one or more matrix processors that perform machine learning operations;” (Paragraph 0054 recites the application existing within a hardware accelerator, where a load balancer can distribute work to one or more VICs (Vision Image Compositors) (multimedia hardware accelerator), one or more DPUs, and one or more GPUs to perform various operations of the application. Paragraph 0360 recites a deep learning application processor that performs matrix multiply operations (one or more matrix processors that perform machine learning operations).)
“performing a first set of operations using the multimedia hardware accelerator of the first compute cluster and the retrieved multimedia data, (Paragraph 0002 recites many processing elements having specific requirements of resolution and format for a video frame, meaning a number of transformations must be performed on video frames in the processing pipeline. Paragraph 0054 further recites the application (performing the transformations using the retrieved multimedia data) existing within a hardware accelerator, where a load balancer can distribute work to one or more VICs (Vision Image Compositors), akin to performing a first set of operations using a multimedia hardware accelerator.)
wherein the first set of operations include pre-processing the retrieved multimedia data, (Paragraph 0055 recites various operations are performed on the multimedia data in
order to allow the media to be processed, akin to a first set of operations that includes pre-processing the retrieved multimedia data.)
wherein the multimedia hardware accelerator includes circuit elements that are each
configured to perform a respective operation in the first set of operations;” (Paragraph 0054 further recites the application (performing the transformations using the retrieved multimedia data) existing within a hardware accelerator, where a load balancer can distribute work to one or more VICs (Vision Image Compositors). Paragraph 0369 further recites the system including one or more processors and incorporated within a system-on-a-chip (SOC) integrated circuit. It is inherently understood that a hardware accelerator on an SOC integrated circuit is made up of circuit elements configured in order to perform the disclosed hardware operations, akin to including circuit elements that are each configured to perform a respective operation in the first set of operations.)
“processing, using the one or more matrix processors of the first compute cluster, the pre-processed multimedia data;” (Paragraph 0461 recites tensor cores (processing cores) configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing (processing, using one or more matrix processors of a first compute cluster, the pre-processed multimedia data).)
“and generating, by processing the pre-processed multimedia data, a model trained for predicting features of subsequent multimedia data” (Paragraph 0363 recites the use of a deep learning application processor to train a machine learning model to predict or infer information (generating a model trained for predicting features of subsequent multimedia data) provided to the deep learning application processor (processing the pre-processed multimedia data).)
With respect to Claim 2, 7, and 12:
Gupte teaches:
“wherein the one or more matrix processors of the first compute cluster include a Tensor Processing Unit (TPU)” (Paragraph 0149 recites at least one embodiment where deep learning accelerators (one or more matrix processors) of the hardware acceleration clusters on an SOC integrated circuit (of the first compute cluster) may include one or more Tensor processing units (TPUs).)
With respect to Claim 3, 8, and 13:
Gupte teaches:
“wherein performing the first set of operations using the multimedia hardware accelerator of the first compute cluster comprises:
compressing or decompressing the retrieved multimedia data” (Paragraph 0326 recites a processing unit that performs compression logic to compress and decompress depth or color data that is written to memory.)
With respect to Claim 4, 9, and 14:
Gupte teaches:
“wherein performing the first set of operations using the multimedia hardware accelerator of the first compute cluster comprises one or more of the following:
cropping, rotating, color space conversions, normalization, downscaling, reading to memory, or writing to memory.” (Paragraph 0062 recites various transformations being performed within a hardware accelerator, including modifying a color space of a video frame and/or image (color space conversion).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 5, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gupte et al., (US Patent Application Number US20220035684A1 filed on May 26, 2021, hereinafter “Gupte”), in view of Foote et al., (US Patent Application Number US20040054542A1 filed on September 13, 2002, hereinafter “Foote”).
With respect to Claims 5, 10, and 15:
Gupte teaches:
“wherein performing the first set of operations using the multimedia hardware accelerator of the first compute cluster comprises (i) cropping, (ii) rotating, (iii) color space conversions, (iv) normalization, (v) downscaling, (vi) reading to memory, and (vii) writing to memory.” (Paragraph 0062 recites various transformations being performed within a hardware accelerator, including modifying a color space of a video frame and/or image (color space conversion). Paragraph 0514 recites one embodiment where the resulting image is stored in a cache (writing to memory) or the application may read an image file from a cache (reading to memory) and normalize an image file or convert an image file to an input resolution (downscaling) of a machine learning model.)
Gupte does not appear to explicitly disclose:
“wherein performing the first set of operations using the multimedia hardware accelerator of the first compute cluster comprises (i) cropping, (ii) rotating, (iii) color space conversions, (iv) normalization, (v) downscaling, (vi) reading to memory, and (vii) writing to memory.”
However, Foote teaches:
“wherein performing the first set of operations using the multimedia hardware accelerator of the first compute cluster comprises (i) cropping, (ii) rotating, (iii) color space conversions, (iv) normalization, (v) downscaling, (vi) reading to memory, and (vii) writing to memory.” (Paragraph 0048 recites effects incorporated into images may include cropping and rotating an image.)
It would have been obvious to a person having ordinary skill in the art (PHOSITA) to combine the teachings of Gupte with the teachings of Foote, which are both in the same field of invention. A PHOSITA would have been motivated to modify the multimedia preprocessing operations from Gupte to include the preprocessing operations of cropping and rotating from Foote because cropping and rotating are well-known and conventional image preprocessing operations used to prepare multimedia data for subsequent processing. Overall, this improves the multimedia data for further image processing or machine learning operations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Vibha Bhat whose telephone number is (571)-272-7091. The examiner can normally be reached on Monday – Thursday from 8:00 AM to 5:00 PM EST and every other Friday from 8:00 AM to 4:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mariela Reyes, can be reached at telephone number (571)-270-1006. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300. Information regarding the status of an application may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or (572)-272-1000.
/Vibha Bhat/Examiner
Art Unit 2142
/Mariela Reyes/Supervisory Patent Examiner, Art Unit 2142
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