DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/2/25, 1/29/25, and 4/18/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 11 is objected to because of the following informalities: It is worded weirdly and in a manner that does not flow syntactically. See rejection of claim 11 below for how the Examiner believes the claim was meant to be written. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 11, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bothe (US 2021/0175351).
As to claims 1 and 14, Bothe teaches a semiconductor device and method of making said semiconductor device (fig. 3), comprising:
a substrate (322, [0086]);
a channel layer (324) and a barrier layer (326), the channel layer and the barrier laver sequentially disposed on the substrate in a stacked manner ([0087] and [0089]);
a source (315’), a gate (310), and a drain (315A’) disposed on the barrier layer (326, [0095]);
a backside via (325’) through a region from the substrate to the barrier layer below the source ([0103]); and
a backside conductive layer (335) covering the backside via (325’) and a back surface of the substrate (322), wherein the source (315) is in contact with and connected to the backside conductive layer ([0103]).
As to claim 7, Bothe further teaches the source has a planar structure (fig. 3).
As to claim 11, Bothe further teaches a field plate (360’) that is disposed on a side of the gate (310) that is away from the substrate (322), is located between the gate (310) and the drain (315A’), and overlaps a projection of the gate (fig. 3, [0101]).
Claim(s) 1, 3-6, 8-10, 14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Senda (US 2016/0056273).
As to claims 1 and 14, Senda teaches a semiconductor device and method of making said semiconductor device (figs. 2B and 4C), comprising:
a substrate (11a, [0027]);
a channel layer (11b) and a barrier layer (11c), the channel layer and the barrier laver sequentially disposed on the substrate in a stacked manner ([0027]);
a source (13pc and 13pd, or just 13pc), a gate (14), and a drain (12) disposed on the barrier layer (11c, [0022]);
a backside via (16) through a region from the substrate to the barrier layer below the source ([0022]); and
a backside conductive layer (16) covering the backside via (15) and a back surface of the substrate (11a), wherein the source (13pc and 13pd, or just 13pc) is in contact with and connected to the backside conductive layer ([0022]).
As to claims 3 and 17, Senda further teaches the material of the source comprises at least one of titanium, gold, or platinum ([0028]).
As to claims 4 and 18, Senda further teaches the source comprises at least one conductive layer ([0028], fig. 2B).
As to claims 5 and 19, Senda further teaches the source comprises a first conductive layer and a second conductive layer that are sequentially stacked, the first conductive layer comprises a titanium element, the second conductive layer comprises a gold element, and the first conductive layer is in contact with and connected to the barrier layer ([0028]).
As to claims 6 and 20, Senda further teaches a thickness of each conductive layer is within a range of 1 nm to 10000 nm ([0028]).
As to claim 8, Senda further teaches the source has an opening (the notch in 13pd, fig. 4C), and the opening is located above the backside via (fig. 4C).
As to claim 9, Senda further teaches the semiconductor device further comprises a thickened source (13pd) and the thickened source is disposed on a surface of the source (13pc and 13pd, fig. 4C, [0029]).
As to claim 10, Senda further teaches the semiconductor device further comprises a thickened source (13pd), the thickened source is disposed on a surface of the source (now interpreted as 13pc), and the thickened source (13pd) is in contact with the backside conductive layer through the opening (now the opening between the two sides of 13pc, fig. 4C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 12, 13, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Senda and/or Bothe, as applied to claims 1 and 14.
As to claims 2 and 16, Neither Bothe nor Senda teach a work function of a material of the source is within a range of 4.3 eV to 6 eV. However, Modifying the work function of the source would have been obvious so as to adjust charge injection and reduce contact resistance. If that leads to the range claimed, then that is the result of ordinary skill in the art and not innovation.
As to claims 12 and 13, Bothe teaches all the limitations of the semiconductor device (see claim 1) except for the semiconductor device being part of a package with power amplifier circuit and an antenna. However, Bothe teaches the semiconductor device is an HEMT usable in a power amplifier ([0007], “HEMT device may be advantageously utilized in a power amplifier (PA).”). Bothe also teaches the device generates RF power, for which antennas are used to handle those signals.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the HEMT of Bothe in a power amplifier circuit and antenna, and packaging these components so as to fabricate a well-known chip.
As to claim 15, Bothe teaches the forming a backside via below the source comprises: making, from the back surface of the substrate, a via on a film layer below the source by using a dry etching process to form the backside via ([0127].
Bothe does not teach removing an etching by-product that remains in the backside via through dry etching or wet etching. However, removal of contaminants is known and would have been obvious so as to fabricate a device free of defects.
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
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Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
5/30/26
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