DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, in the reply filed on 1/12/2026. is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Japp (US2011/0284273A1).
Claim 1. A method of forming one or more vias in a packaging substrate, the method comprising:
laminating (see Figs. 3 and 4’; see [0066]) a plurality of layers (37, 35, 21, 35’, 37’ in Fig. 3) of a packaging substrate;
drilling a via hole (41, Fig. 5; see [0068]) through the plurality of layers using a through drill (“mechanical drills or suitable laser equipment” in [0068]), the plurality of layers not including a capture pad or ring along a path of the through drill for drilling the via hole (see Figs. 4 and 5); and
forming a via (45, Fig. 6) in the via hole using a plating process (see [0069]).
Claim 2. The method of claim 1 wherein the through drill is configured to drill through all of the laminated plurality of layers. This is evident from the fact that the hole 41 has been formed.
Claim 3. The method of claim 1 wherein the through drill includes a mechanical drill (“mechanical drills” in [0068]).
Claim 4. The method of claim 1 wherein the through drill includes a laser drill (“laser equipment” in [0068]).
Claim 5. The method of claim 1 wherein the via is configured to reduce signal reflection of analog signals along a path of the via. Since the same structure as that claimed is being formed, it has the same properties.
Claim 6. The method of claim 1 further comprising forming a plurality of stacked vias in the packaging substrate. Refer to annotated Fig. 7, below. Though Japp mentions Fig. 7 shows various types of thru holes, Japp does not explicitly describe the identified elements as stacked vias, but it is readily apparent to one of ordinary skill in the art that the identified elements are vias which will be stacked, in the final assembly.
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Claim 7. The method of claim 1 wherein the plating process includes copper plating (see [0069]).
Claim 8. The method of claim 1 wherein the packaging substrate includes one or more layers (53, Fig. 7) in addition to the plurality of layers and wherein the via does not extend through the one or more layers.
Claim 9. A method of forming one or more vias in a packaging substrate, the method comprising:
laminating (see Figs. 3 and 4’; see [0066]) a plurality of layers (37, 35, 21, 35’, 37’ in Fig. 3) of a packaging substrate;
drilling a via hole (41, Fig. 5; see [0068]) through the plurality of layers using a through drill (“mechanical drills or suitable laser equipment” in [0068]), the plurality of layers not including a feature along a path of the through drill for drilling the via hole (see Figs. 4 and 5); and
forming a via (45, Fig. 6) in the via hole using a plating process (see [0069]).
Claim 10. The method of claim 9 wherein the through drill is configured to drill through all of the laminated plurality of layers. This is evident from the fact that the hole 41 has been formed.
Claim 21. The method of claim 9 wherein the through drill includes a mechanical drill (“mechanical drills” in [0068”).
Claim 22. The method of claim 9 wherein the through drill includes a laser drill (“laser equipment” in [0068]).
Claim 23. The method of claim 9 wherein the via is configured to reduce signal reflection of analog signals along a path of the via. Since the same structure as that claimed is being formed, it has the same properties.
Claim 24. The method of claim 9 further comprising forming a plurality of stacked vias in the packaging substrate. Refer to annotated Fig. 7, above. Though Japp mentions Fig. 7 shows various types of thru holes, Japp does not explicitly describe the identified elements as stacked vias, but it is readily apparent to one of ordinary skill in the art that the identified elements are vias which will be stacked, in the final assembly.
Claim 25. The method of claim 9 wherein the plating process includes copper plating. See [0069].
Claim 26. The method of claim 9 wherein the packaging substrate includes one or more layers (53) in addition to the plurality of layers and wherein the via does not extend through the one or more layers. See Fig. 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 24 are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Japp in view of Kumar (US2011/0289774A1).
Regarding claims 6 and 24, if Applicant disagrees, the identified features are stacked vias, such features are, nevertheless, conventional. See for example stacked vias 150 in Figs. 4a and 5. As is evident from Fig. 4a, the substrates 70-1 are analogous to substrates 53 of Japp. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form in substrates 53 vias which are stacked vias in the final structure of Fig. 7, as stacked vias are conventional interconnect structures, for providing an electrical connection between several circuit layers.
Conclusion
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
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