DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-10, 21-23 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anstrom (US2002/0100613A1).
Anstrom discloses the claimed invention as follows:
Claim 1. A method of forming one or more vias in a packaging substrate, the method comprising:
laminating (see Fig. 8 and [0062]) a plurality of layers (all of the layers of Fig. 7, plus a layer 120 and a layer 130 as shown in Fig. 8; see [0067] describing laminating these layers together) of a packaging substrate at the same time, the plurality of layers including an upper side (upper side of 120) and a lower side (lower side of 120) configured for mounting one or more components and forming an overmold (components can be mounted thereon, and a overmold can be formed);
drilling a via hole (hole for PTH 140, Fig. 8, but through the whole stack of layers, as described in [0067]) through the laminated plurality of layers using a through drill continuously (see [0064] and [0067]), the laminated plurality of layers not including a capture pad or ring (see Fig. 8; see [0064] explicitly mentioning the PTH 140 as shown is not electrically connected to any of substructures 71-77, even though it may be connected to some or all) along a path of the through drill for drilling the via hole, the via hole extending through all of the laminated plurality of layers including the upper side and the lower side; and
forming a via in the via hole using a plating process (140 is a PTH, i.e. plated through-hole).
Claim 2. The method of claim 1 wherein the through drill is configured to drill through all of the laminated plurality of layers. See [0064] and [0067].
Claim 3. The method of claim 1 wherein the through drill includes a mechanical drill. See “mechanical … drilling” in [0064].
Claim 4. The method of claim 1 wherein the through drill includes a laser drill. See “laser drilling” in [0064].
Claim 5. The method of claim 1 wherein the via is configured to reduce signal reflection of analog signals along a path of the via.
Claim 8. The method of claim 1 further comprising forming a second via (e.g. 124, Fig. 9; see [0067] and [0068]) that does not extend through all of the plurality of layers.
Claim 9. A method of forming one or more vias in a packaging substrate, the method comprising:
laminating (see Fig. 8 and [0062]) a plurality of layers (all of the layers of Fig. 7, plus a layer 120 and a layer 130 as shown in Fig. 8; see [0067] describing laminating these layers together) of a packaging substrate at the same time, the plurality of layers including an upper side (upper side of 120) and a lower side (lower side of 120) configured for mounting one or more components and forming an overmold (components can be mounted thereon, and a overmold can be formed);
drilling a via hole (hole for PTH 140, Fig. 8, but through the whole stack of layers, as described in [0067]) through the laminated plurality of layers using a through drill continuously (see [0064] and [0067]), the laminated plurality of layers not including a feature (see Fig. 8; see [0064] explicitly mentioning the PTH 140 as shown is not electrically connected to any of substructures 71-77, even though it may be connected to some or all) along a path of the through drill for drilling the via hole, the via hole extending through all of the laminated plurality of layers including the upper side and the lower side; and
forming a via in the via hole using a plating process (140 is a PTH, i.e. plated through-hole).
Claim 10. The method of claim 9 wherein the through drill is configured to drill through all of the laminated plurality of layers. See [0064] and [0067].
Claim 21. The method of claim 9 wherein the through drill includes a mechanical drill. See “mechanical … drilling” in [0064].
Claim 22. The method of claim 9 wherein the through drill includes a laser drill. See “laser drilling” in [0064].
Claim 23. The method of claim 9 wherein the via is configured to reduce signal reflection of analog signals along a path of the via. Given that it has the same structure as claimed, the PTH 140 is configured as claimed.
Claim 26. The method of claim 9 further comprising forming a second via (e.g. 124, Fig. 9; see [0067] and [0068]) that does not extend through all of the plurality of layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-10, 21-23, 25 and 26 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Anstrom.
Anstrom discloses the claimed invention, as detailed above. As described in [0067], dielectric sheets 122 and 132 without metallization are compressed with the other layers during the laminating. The through hole for PTH 140 is formed after the compression, as are microvias. It is understood from [0067] that the through hole for PTH 140 would not be passing through any capture pads or rings or features, because the dielectric layers 122 and 132 do not include any metallization as laminated. However, if Applicant disagrees, the claimed invention would have, nevertheless, been obvious. Specifically, [0068] described the drilling to form the holes for the microvias, electroless plating of copper, and electroplating to form the plated layer for the microvias. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form PTH 140 at the same time, i.e. first drill all the holes for all the microvias and for PTH 140, followed by electroless plating for the microvias and for PTH 140, and electroplating to form the plated layer for all the microvias and for PTH 140, to avoid separate processing steps for features that can be created in the same operation.
Regarding claims 7 and 25, Anstrom does not explicitly mention the plating for PTH 140 being copper plating, but does disclose copper plating for the microvias (see [0068]). One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious and with predictable results to utilize copper for the plating of PTH 140, since copper is already used in the rest of the circuit substrate, including for plating of other vias.
Claims 6 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Zollo (CN110691466A) in view of Anstrom.
Zollo discloses (limitations not disclosed are crossed out, below) a method of forming one or more vias in a packaging substrate, the method comprising:
laminating (see Fig. 6A and [0038]) a plurality of layers (all layers of Fig. 6A) of a packaging substrate at the same time, the plurality of layers including an upper side and a lower side configured for mounting one or more components and forming an overmold (components can be mounted thereon, and a overmold can be formed);
drilling a via hole (72, Fig. 6C; see [Fig. 5B and [0035]-[0036] discussing drilling of the various vias; the embodiment of Fig. 6C is formed the same way) through the laminated plurality of layers using a through drill continuously,
forming a via (74, Fig. 6D; see [0039]) in the via hole using a plating process; and
forming a plurality of stacked vias (see various two-via stacks in Fig. 6D) in the packaging substrate.
Zollo discloses the claimed invention, except the hole 72 is shown as passing through various conductive features. However, it is known in the art to form holes not passing through any conductive features in a multilayer laminate, for example when the plated through hole is only intended to connect to other elements at its two ends. Anstrom, for example, teaches a plated through hole 140 not connected to any of the conductive layers in a laminated substrate (see Fig. 9 and [0067]), but also teaches the PTH could be connected to some or all conductive layers (see [0064]).
Taking into consideration the teachings of Zollo and Anstrom, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that whether or not a hole for a through hole passes through any conductive features is a design consideration, and it would have been equally obvious to implement a through hole connected to all, some, or none of the conductive layers in a laminated stack.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US6495239B1 is another reference teaching a plated through hole (600) passing through a multilayer substrate, without being connected to any of the conductive layers along the path of the hole.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
Prosecution Insights