DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/10/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai et al. (US 20100245160) in view of Dalla Longa et al. (US 11245410).
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With respect to claim 1, Sakurai et al. (US 20100245160) discloses a charge pump, comprising: a first current digital to analog converter (CURRENT DAC_U; 407B) connected to a supply voltage terminal and comprising a first variable resistor (407B) having a first resistance (resistance through the switches) configurable based on a first digital control code (ERROR); and a first terminal (bottom of 407b); a first switch (one of the oscillator switches) and connected to an output terminal ( at FMCW signal); a second current digital to analog converter (CURRENT DAC_D; 407C) connected to a reference voltage terminal (GROUND) and comprising a second variable resistor (407c) having a second resistance (resistance through the switches) configurable based on a second digital control code (ERROR); and a second terminal (top of 407c); and a second switch (second switch of the oscillator switches) connected and connected to the output terminal (at FMCW signal), wherein: the first current digital to analog converter sources a first current at the first terminal based on the first resistance responsive to the first switch being closed; and the second current digital to analog converter sinks a second current at the second terminal based on the second resistance responsive to the second switch being closed but fails to disclose the first switch connected directly to the first terminal and connected to the output terminal and the second switch directly to the second terminal and connected to the output terminal.
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Fig. 5A of Dalla Longa et al. (US 11245410) teaches a current DAC showing the details of the current DAC having a first terminal (n1c) and a switch (i.e. M3, M4 or M5) connected to the first terminal and connected directly to the output terminal (n1c and n2c would be considered the output terminal) and a second switch (i.e. M6, M7 or M8) connected directly to the second terminal (n2c) and connected to the output terminal (n1c and n2c would be considered the output terminal) with Ip sourced at the first terminal and In sinks a second current at the second terminal.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the invention and teachings in fig. 5A of Dalla Longa et al. in the circuit of Sakurai et al. for the purpose of results in smaller circuit area and additional power savings (see Col. 11 lines 49-52).
With respect to claim 8, the circuit above discloses a phase locked loop, comprising: a voltage controlled oscillator (401) configured to generate an output signal (FMCW signal); a loop filter (capacitor at 407A) connected to the voltage controlled oscillator; a phase frequency detector (402) configured to generate a first signal (jscw_fall) responsive to the output signal having a frequency greater than a frequency reference and to generate a second signal (scw_rise) responsive to the output signal having a frequency less than the frequency reference; and a charge pump (integrator/ figure 10) connected to the loop filter (capacitor at 407a) and comprising: a first current digital to analog converter(current DAC U) connected to a supply voltage terminal and comprising a first resistance (through switches) configurable based on a first digital control code (ERROR); and a first terminal (bottom of 407b in Sakurai, n1c in Dalla Longa et al.) ; a first switch (one of the switches in oscillator, Sakurai, M3, M4 or M5 Dalla Longa) controlled by the first signal and connected directly to the first terminal and connected to the loop filter; a second current digital to analog converter (CURRENT DAC_D; 407C) connected to a reference voltage terminal (at ground) and comprising a second variable resistor having a second resistance (resistance through the switches) configurable based on a second digital control code (ERROR); and a second terminal (top of 407c in Sakurai, n2c in Dalla Longa et al.); a second switch (one of the switches in oscillator, Sakurai, M6, M7 or M8 Dalla Longa) controlled by the second signal and connected directly to the second terminal and connected to the loop filter and the second current digital to analog converter (Current DAC_D), wherein: the first current digital to analog converter sources a first current at the first terminal based on the first resistance responsive to the first switch being closed; and the second current digital to analog converter sinks a second current at the second terminal based on the second resistance responsive to the second switch being closed.
With respect to claim 15, the combination above produces a method, comprising: generating an output signal (FMCW signal) in an oscillator (401) based on a control voltage (Voltage control voltage); generating the control voltage in a loop filter (loop filter at 407A); generating a first signal (jscw_fall) responsive to the output signal having a frequency greater than a frequency reference; generating a second signal (scw_rise) responsive to the output signal having a frequency less than the frequency reference; configuring a first resistance (through the switches) of a first current digital to analog converter (Current DAC U) connected to a supply voltage terminal based on a first digital control code (ERROR); configuring a second resistance (resistance through switches) of a second current digital to analog converter (CURRENT DAC D) connected to a reference voltage terminal based on a second digital control code (ERROR); closing a first switch (one of the switches in oscillator, Sakurai, M3, M4 or M5 Dalla Longa) connected directly to a first terminal of the first current digital to analog converter and connected to the loop filter based on the first signal to source a first current at the first terminal based on the first resistance; and closing a second switch (one of the switches in oscillator, Sakurai, M6, M7 or M8 Dalla Longa) connected to the loop filter and connected directly to a second terminal of the second current digital to analog converter based on the second signal to sink a second current at the second terminal based on the second resistance.
Allowable Subject Matter
Claims 2-7, 9-14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art of record fails to suggest or disclose the charge pump of claim 1, wherein: the first current digital to analog converter comprises: a first amplifier having a first input connected to a first voltage reference, a second input, and an output; and a first transistor controlled by the output of the first amplifier connected between the first switch and the first variable resistor and connected to the second input of the first amplifier.
Here, the first amplifier and a first transistor are not as disclosed in the claim language.
With respect to claim 5, the prior art of record fails to suggest or disclose a third current digital to analog converter connected to the first current digital to analog converter and the second current digital to analog converter and having a third resistance configurable based on a third digital control code, wherein: the third current digital to analog converter sources a third current based on the third resistance responsive to the first switch being closed; and the third current digital to analog converter sinks a fourth current based on the third resistance responsive to the second switch being closed.
Here, the third resistance is not based on a third digital control code within a second current digital to analog converter as described in the claim.
With respect to claim 9, the prior art of record fails to suggest or disclose the phase locked loop of claim 8, wherein: the first current digital to analog converter comprises: a first amplifier having a first input connected to a first voltage reference, a second input, and an output;; and a first transistor controlled by the output of the first amplifier connected between the first switch and the first variable resistor and connected to the second input of the first amplifier.
Here, the first amplifier and a first transistor are not as disclosed in the claim language.
With respect to claim 16, the prior art of record fails to suggest or disclose the
method of claim 15, wherein: the first current digital to analog converter comprises: a first amplifier having a first input connected to a first voltage reference, a second input, and an output; and a first transistor controlled by the output of the first amplifier connected between the first switch and the first variable resistor and connected to the second input of the first amplifier.
Here, the first amplifier and a first transistor are not as disclosed in the claim language.
With respect to claim 19, the prior art of record fails to suggest or disclose comprising: configuring a third resistance of a third current digital to analog converter connected to the supply voltage terminal and the reference voltage terminal based on a third digital control code; closing the first switch to source a third current in the third current digital to analog converter to the loop filter based on the third resistance; and closing the second switch to sink a fourth current in the third current digital to analog converter from the loop filter based on the third resistance.
Here, the third resistance of the third current digital to analog converter is not based on the third digital control code and does not and open the switches as disclosed.
Claims 3-4, 6-7, 10-14, 17-18 and 20 include the above-described allowable subject matter and are objected to for being dependent on dependent Claims 2, 5, 9, 16 and 19.
Response to Arguments
Applicant’s arguments, see pages 1-3 in Remarks, filed 2/10/2026, with respect to the rejection(s) of claim(s) 1, 8 and 15 under 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sakurai in view of Della Longa.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
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