DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Response to Arguments
Applicant's arguments filed 26 February 2026 have been fully considered but they are not persuasive.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Specifically, Applicant does not show how the amendments to claim 13 overcome the prior art cited in the previous office action. Applicant has amended independent claim 13 to include limitations previously presented in dependent claim 14. However, the amended limitations from claim 14 were previously rejected using the combined teachings of US Patent No. 11,163,453 (hereinafter Jo) and US Patent Application Publication No. 2002/0108021 (hereinafter Syed). Applicant has not shown or described how the amendment overcomes or distinguishes over the cited prior art. The Examiner maintains that the cited prior art teaches the limitations of amended claim 13. Specifically, Syed shows that a DMA controller is configured to perform DMA operations on memory islands of a memory sub-system that are outside of an active subset of memory islands (Syed; Abstract). Therefore, the Examiner maintains that the prior art of record teaches all the limitation of independent claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,163,453 (hereinafter Jo) in view of US Patent Application Publication No. 2002/0108021 (hereinafter Syed).
As per claim 13, Jo teaches a computing system, comprising: a host system (Jo; Figure 5 Item 310); a memory sub-system (Jo; Figure 5 Item 330) having a plurality of memory islands (Jo; Figure 5 Items 331 – 336); an interconnect (Jo; Figure 5 “CH1” – “CH4”) configured between the host system and the memory sub-system and having a communication bandwidth; wherein the interconnect is configured to allocate portions of the communication bandwidth to an active subset of the plurality of memory islands (Jo; Col 8 Lines 15 – 51).
Jo does not teach wherein the memory sub-system includes a direct memory access controller; wherein the direct memory access controller is configured to perform direct memory access operations on memory islands of the memory sub-system but outside of the active subset.
However, Syed teaches a memory sub-system including a direct memory access controller (Syed; Abstract); and wherein the direct memory access controller is configured to perform direct memory access operations on memory islands of the memory sub-system but outside of the active subset (Syed; Abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Jo to include the DMA controller because doing so allows for loading data to the memory in parallel with other accesses (Syed; Paragraph [0080]).
Claim(s) 14 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,163,453 (hereinafter Jo) in view of US Patent Application Publication No. 2002/0108021 (hereinafter Syed), and further in view of US Patent No. 10,547,403 (hereinafter Olson).
As per claim 14, Jo in combination with Syed teaches the invention as described per claim 13 (see rejection of claim 13 above).
Jo in combination with Syed does not teach wherein the interconnect includes a photonic interconnect.
However, Olson teaches a system interconnect using a photonic interconnect (Olson; Abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Jo in combination with Syed to include the photonic interconnect because doing so allows for increased bandwidth over existing networks (Olson; Col 6 Lines 5 – 12).
As per claim 15, Olson also teaches wherein the photonic interconnect includes a photonic switch having at least an optical demultiplexer or an optical multiplexer (Olson; Col 7 Lines 16 – 25).
As per claim 16, Olson also teaches wherein the photonic switch is implemented using an arrayed waveguide grating (AWG) (Olson; Col 7 Lines 16 – 25).
Allowable Subject Matter
Claims 1 – 12 and 17 – 20 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1 – 12 are allowable because the prior art of record fails to teach or suggest alone or in combination receiving, from the host system, an indication of completion of computations performed using memory resources provided using a second memory island that is currently in the active subset, as required by independent claim 1, in combination with the other claimed limitations (emphasis added). The prior art of record teaches performing a DMA transaction on an inactive memory island (Syed) in order to pre-load and unload data from the memory (Syed; Abstract), but does not teach the indication of the completion of computations performed using memory resources provided using a second memory island that is in the active subset of memory islands, as required by independent claim 1.
Claims 2 – 12 are also allowable because of their dependence, either directly or indirectly, upon allowable independent claim 1.
Claims 17 – 20 are allowable because the prior art of record fails to teach or suggest alone or in combination scheduling workloads of a plurality of processing elements in a host system running one or more applications using memory provided by an active subset of a plurality of memory islands, the plurality of memory islands including a first memory island that is not currently in the active subset and a second memory island that is currently in the active subset; and sending, based on the scheduling and to a direct memory access controller, a first instruction to load first data into a memory address region currently being implemented via the second memory island in the active subset, causing the direct memory access controller to allocate the first memory island as a replacement of the second memory island and load the first data from a data store into the first memory island, as required by independent claim 17, in combination with the other claimed limitations (emphasis added). The prior art of record teaches performing a DMA transaction on an inactive memory island (Syed) in order to pre-load and unload data from the memory (Syed; Abstract), but does not teach the scheduling of the workloads in combination with the sending instructions to load data into the memory address region and allocating the first memory island as a replacement for the second memory island, as required by independent claim 17.
Claims 18 – 20 are also allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 17.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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