DETAILED ACTION
This action is in response to communication filed on 3/13/2024.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3, 10, and 17 are objected to because of the following informalities: For claims 3, 10, and 17, on line 1, “wherein relaxed range” should be --wherein the relaxed range--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-12 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura et al. (US 2021/0216473).
Regarding claim 1, Kimura discloses a computing system, comprising: one or more processors; and memory storing an application which, when executed by the one or more processors, performs an operation, the operation comprising:
generating a relaxed range for a data operation (Kimura discloses generating parameter (location, maxsize, length) that define a relaxed range for the write data operation in SlottedAppend, where the atomic reserves space within the range for the payload; see [0035] “Many data structures in database systems, including disk pages, are split in variable-length slots which are accessed through indirection. The simplest form of such an indirection is an offset field that points to the first byte of the entry as a function of the location of the offset. The SlottedAppend RDMO safely manipulates such structures in a single network request. The pseudocode is as follows…”);
generating a packet that combines an atomic operation with the data operation (Kimura disclose generating a single network request (packet) for SlottedAppend that combines an atomic featch-and-add with a data write (memcpy); see [0038] “one usage example for SlottedAppend in an OLTP workload is inserting one tuple 108 in a page 104, as shown in FIG. 1. The corresponding page 104 is first located in memory. Then SlottedAppend atomically increments the free pointer 102 using a fetch-and-add operation and writes the data to the slotted page 104 in one network operation”); and
transmitting the packet on a network (Kimura discloses transmitting the RDMO (combined operation) over the network to the remote node; see [0021] “an RDMO may be a short sequence of reads, writes and atomic memory operations that will be transmitted and executed at the remote node without interrupting the remote CPU, similar to an RDMA Read or RDMA Write operation”).
Regarding claim 2, Kimura discloses the computing system of claim 1, wherein the relaxed range comprises a beginning address and an ending address related to a size of a payload of the data operation (Kimura discloses the relaxed range with beginning (location + write_offset - length) and ending (location + write_offset) addresses derived from the payload size (length); see [0035] “size_t write_offset = atomic_fetch_add(location, length); if (wrlte_offset > maxsize){ atomic_fetch_add(locaton, −length); return maxsize; } memcpy (location + write_offset − length, buffer, length)” ).
Regarding claim 3, Kimura discloses the computing system of claim 1, wherein relaxed range comprises a tuple that includes a destination base address, a destination end address, and an ID of a destination node for the packet (Kimura discloses the SlottedAppend parameters as a tuple with destination base address (location), destination end address (maxsize), and destination node ID implied in the RDMA context (e.g., remote node connection); see [0035] “size_t SlottedAppend (void* location, size_t maxsize, const void* buffer, size_t length)”).
Regarding claim 4, Kimura discloses the computing system of claim 1, wherein the atomic operation obtains a lock of data associated with the data operation (Kimura discloses the atomic fetch-and-add obtains a lock on the reserved buffer slot for the data write; see [0035] “the SlottedAppend RDMO safely manipulates such structures in a single network request” and [0037] “it shrinks the conflict window and permits more concurrency under contention over an RDMA-only implementation” ).
Regarding claim 5, Kimura discloses the computing system of claim 4, wherein the data operation is a put operation that stores data in a buffer at a destination node after the lock is obtained (Kimura discloses the data operation as a put (memcpy write) that stores the buffer payload at the remote node after the atomic lock/reservation since the write occurs only after successful atomic reservation and stores data in the remote buffer post-lock; see [0035] “if (wrlte_offset > maxsize){ atomic_fetch_add(locaton, −length); return maxsize; } memcpy (location + write_offset − length, buffer, length)”).
Regarding claim(s) 8-12 and 15-18, do(es) not teach or further define over the limitation in claim(s) 1-5 and 1-5 respectively. Therefore claim(s) 8-12 and 15-18 is/are rejected for the same rationale of rejection as set forth in claim(s) 1-5 and 1-5 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7, 13-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (US 2021/0216473) in view of Parthasarathy et al. (US 2002/0184392).
Regarding claim 6, Kimura discloses the invention substantially, however the prior art does not explicitly disclose the computing system of claim 1, wherein the packet contains an extended transport header (ETH) indicating that the packet contains an atomic operation.
Parthasarathy in the field of the same endeavor discloses techniques for a multi-headed network interface controller that enables direct RDMA data transport to accelerator memory in heterogenous computing environments by bypassing host fabrics and using address translation for efficient packet routing. In particular, Parthasarathy discloses the following:
wherein the packet contains an extended transport header (ETH) indicating that the packet contains an atomic operation (Parthasarathy [0043] “The Atomic extended transport header 330 contains additional transport fields for atomic packets and atomic operations”).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively filed to modify the prior art with the teaching of Parthasarathy to incorporate techniques for a multi-headed network interface controller that enables direct RDMA data transport to accelerator memory in heterogenous computing environments. One would have been motivated to combine the prior art with the teaching of Parthasarathy to enable more efficient direct RDMA transport and address translation in heterogenous datacenter environment, thereby reducing latency and bypassing host fabrics for atomic-data combined operations.
Regarding claim 7, Kimura-Parthasarathy discloses the computing system of claim 6, wherein the ETH comprises a header that includes an atomic virtual address that specifies an address for an atomic operation and a base virtual address that specifies a first memory word of a buffer where data should be read from, or written to, at a destination node (Parthasarathy [0043] “The Atomic extended transport header 330 contains additional transport fields for atomic packets and atomic operations. For example, the Atomic extended transport header 330 may include, but not limited to, a Virtual Address (VA) field 347 used to provide the remote Virtual Address, a Remote Key (Rkey) field 348 used to authorize access to the remote Virtual Address; and a swap and compare data field 349 used to provide operands in atomic operations”).
Regarding claim(s) 13-14 and 19-20, do(es) not teach or further define over the limitation in claim(s) 6-7 and 6-7 respectively. Therefore claim(s) 8-12 and 15-18 is/are rejected for the same rationale of rejection as set forth in claim(s) 6-7 and 6-7 respectively.
Conclusion
For the reason above, claims 1-20 have been rejected and remain pending.
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JIMMY H TRAN
Primary Examiner
Art Unit 2451
/JIMMY H TRAN/Primary Examiner, Art Unit 2451