DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 03/13/2024 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over OGURA (U.S. 2018/0224876)
Regarding claim 1, OGURA (hereinafter, Ref~876) discloses (please see Fig. 9 and related text for details) a semiconductor device (device from Fig. 9), comprising:
an output terminal (OUT of Fig. 9) that outputs an output voltage (Vout of Fig. 9);
a bipolar transistor (please note that FET are being used instead of the claimed BJT. However, it would have been obvious to one skilled in the art to choose/replace BJTs over FETs in order to handle larger current and/or to obtain higher gain at least) that outputs a collector current according to an amount of a base current and supplies the collector current to an output node to which the output terminal is connected;
a bias current generation part (Pm/18/SW1/14 of Fig. 9 can be read as the claimed part) that comprises a first node (see common node of 12/14/N1/N2 of Fig. 9), a first constant current source (12 of Fig. 9) connected to the first node, and a first transistor (please note that SW1 of Fig. 9 would likely be N type transistor as shown in various embodiments, for instance, see N3 of Fig. 7) connected in parallel with the first constant current source with respect to the first node, and generates (via drain of transistor SW1 of Fig. 9) a bias current;
a differential input part (centered by N1/N2/P1/P2 of Fig. 9) that comprises a differential pair (N1/N2 of Fig. 9) and a second node (node V2 of Fig. 2 ), wherein a current corresponding to the bias current generated by the bias current generation part flows through the differential pair, and a reference voltage (VREF of Fig. 9) and a voltage (VFB of Fig. 9) corresponding to the output voltage are input to the differential pair, and the differential pair generates at the second node a control voltage (V2 of Fig. 9) according to a difference between the reference voltage and the voltage corresponding to the output voltage; and
a drive part (P3/34 of Fig. 9) that comprises a current supply circuit (34 of Fig. 9), a third node (V3 of Fig. 9) to which a base of the bipolar transistor is connected, and a second transistor (P3 of Fig. 9) controlling a potential of the third node according to the control voltage, wherein the first transistor controls the bias current generated by the bias current generation part according to the control voltage of the differential input part as seen, meeting claim 1.
Regarding claim 9, Ref~876 discloses the semiconductor device according to claim 1, wherein the current supply circuit of the drive part is a constant current source or a resistor as seen, meeting claim 9.
Regarding claim 10, Ref~876 supports the claimed “wherein the differential input part decreases a current flowing through the first transistor to decrease the bias current of the bias current generation part in response to a load (LOAD 2 of Fig. 9) connected to the output terminal changing to a light load, and increases the current flowing through the first transistor to increase the bias current of the bias current generation part in response to the load connected to the output terminal changing to a high load”, since it is configured in the same manner compared to the claimed one, meeting claim 10.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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