DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8-15 and 18-19 have been examined.
The objections and rejections from previous office action that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 112
Claim 1 is rejected under 112(b) for a term “by the computer device” as being lacked of antecedent basis.
Claims 2-6 and 8-9 are rejected based on dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 8-9, 10, 13-14, 19 are rejected under 35 U.S.C. 102 as being anticipated by Remis et al. (20180081849 A1), hereinafter known as Remis et
Regarding claims 1, 10, Remis teaches a method and an apparatus performed by a computing device, and the method comprising: storing, by the computer in a persistence storage area of the computing devices (see par 75-77), a correspondence between a peripheral component interconnect express (PCIE) device identifier and an identifier of a port on the computing device (see fig. 1A, 114a-n, 117a-n, par. 41, wherein each identified 114 is connecting to each identified ports 117), wherein the correspondence is stored in a persistent storage area of the computing device (see par. 38, par. 77, 38, wherein the mapping data for 117 port id and 114 PCIe mapping information stored in memory 108;
Determining, by the computer device, a first port that connects a first PCIE device to the computing device (see figure 5, step 502, determining each 114 connecting to port 117); and
allocating a first PCIE device identifier to the first PCIE device based on a first identifier of the first port and the correspondence stored in the persistence storage area of the computing device (see figure 5, step 504 and par. 68, wherein data module 230 determines the installation location identifiers for each 114).
Regarding claims 4 and 13, Remis teaches wherein a process of storing the correspondence comprises: obtaining a configuration file that comprises the correspondence; and storing the configuration file in the persistent storage area of the computer device (see fig. 3, 300, wherein apparatus 300 contains configuration files is utilized such as data module 230, verification modules 235, notification module 240, identifier module 310, reference to configure connections 114 to a computer system 100).
Regarding claims 5 and 14, Remis teaches wherein the obtaining the configuration file comprises: generating the configuration file based on a configuration operation in a configuration interface for the correspondence; or receiving a configuration file through an interface (see par. 30, 54, Remis teaches the cable management apparatus 110 is configured such programming, software modules, user selections).
Regarding claims 8 and 18, Remis teaches where the correspondence is stored in a baseboard manager controller (BMC) of the computer device (see par. 52, BMC 113).
Regarding claims 9 and 19, Remis teaches where the method is implemented by a basic input/output system (BIOS) of the computer device (see par. 39 BIOS 106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Remis in view of Shao et al. (US 20150293873), hereinafter referred to as Shao.
Regarding claims 2 and 11, Remis teaches wherein the allocating the first PCIE device identifier to the first PCIE device based on the first identifier of the first port (see figure 1A, wherein each 114 identified installed corresponding to 117 ports) and the correspondence comprises: looking up the correspondence based on the first identifier of the first port to obtain the first PCIE device identifier allocated to the first PCIE device (see par 78, wherein module 310 uses the FPGA 204, SEP 115, BMC 113 to assign the installation location for each), ;
writing the first PCIE device identifier allocated to the first PCIE device into a temporary storage area in the computing device (see par. 77, wherein the module 310 write the installation location identifier for each 114 to a storage location includes a register, cache, a non-volatile memory device, a volatile memory device); and
Remis does not expressly teach registering, by using a driver corresponding to the first PCIE device, the first PCIE device identifier of the first PCIE device stored in the temporary storage area with an operating system of the computing device. However, Shao teaches load a right driver of the PCIe device discovered in the computer system (see par. 112-113). The CPU in the system may further search a pre-configured device driver for a device driver of the PCIe device based on device identifier, vendor ID (see par. 113). Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art to combine the teaching of Shao into Remis because the device drivers provide a critical link between hardware and software, enabling computers to utilize their device effectively in data communications, thus it would improve performance stability, and compatibility.
Regarding claims 3 and 12, Remis teaches wherein the temporary storage area comprises a register configured based on a peripheral component interconnect (PCI) standard or a PCIE standard (see par. 77 and par. 27, wherein Ramis listed examples (a non-exhaustive list) of storage device which includes RAM).
Claims 6, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Remis in view of Cepulus et al. (US patent 6,397,268), hereinafter referred to as Cepulus.
Regarding claims 6 and 15, Remis does not explicitly teach wherein the obtaining the configuration file comprises: obtaining historical allocation data, wherein the historical allocation data comprises the port through which the computing device is connected to the PCIE device in a historical period of time and the PCIE device identifier allocated to the PCIE device in the historical period of time; and generating the configuration file based on the historical allocation data. However, Cepulis teaches prior configuration information stored in the NVAM and if no new device is added to the system, the POST routine depends on prior information stored in the NVRAM by the system configuration utility (see par. 11-12, claim 20). Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art to combine the teaching of Cepulis to utilize previous configuration to save time from re-run unnecessary steps, thus enhancing Remis system performance.
Response to Argument
Applicant argues that Remis step 502 does not teach determining a first port that connects to a first PCIE device to the computing device by traversing ports on the computing device in a start process.
Examiner disagrees, in the office, examiner cited figure 5, step 502, determining each 114 connecting to port 117). Examiner also cited fig. 1A, 114a-n, 117an-n in the claim rejections 1, 10 and 17. Any devices 114 can be interpreted as a first PCIE, in this mapping device 114a could be mapped as a first device. As for the ports 117a-n, can also be interpreted as a first port, thus Remis teaches 502 teaches determining first device 114a connecting to port 117a. Further, see par. 74 teaches each device 114 has a slot identifier, a bay number, a PCIe lane identifier for identifying connections. Furthermore, the newly amendment “by traversing ports on the computing device in a start process”. This newly amendment is interpreting in the same meaning supported in the current specification in paragraph 51 i.e. traversing as the same as enumerate on a computer system in a start process. Remis, teaches this newly amendment as disclosed in figure 5, figure 5 disclosed a beginning step for a determining each communication bus coupled to a peripheral device with a start and configuring devices connection.
Applicant argues that Remis teaches step 514 does not teach “allocating, based on a corresponding stored in the persistent storage areas and a first identifier of a first port” because step 514 is generating the mapping after the identifier is assigned at step 504.
Examiner disagrees, par 75-77, Remis also teaches that those peripheral devices 114a-n, 117a-n ports are pre-configured identifiers and stored them in a storage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tim Vo whose telephone number is (571)272-3642. The examiner can normally be reached on Monday-Thursday 5:30 AM - 4:00 PM.
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/TIM T VO/Supervisory Patent Examiner, Art Unit 2138