DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7 and 16-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by TAJIRI (US Patent Appl. Pub. No. 2024/0071875 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
[Re claim 1] TAJIRI discloses the semiconductor device comprising: a substrate (11) including an obverse surface (11A) facing in a thickness direction; a lead (23 and 24) including a die pad portion (211) bonded to the substrate and a terminal portion (212 and 222) connected to the die pad portion; a semiconductor element (31 and 32) bonded to the die pad portion; and a bonding layer (13) interposed between the obverse surface (11A) and the die pad portion (211), wherein the obverse surface (11A) includes a first edge (D1) extending in a first direction orthogonal to the thickness direction and a second edge (D2) extending in a second direction orthogonal to the thickness direction and the first direction, as viewed in the thickness direction, the terminal portion (212 and 222) protrudes outward from the obverse surface relative to the first edge, and a distance from the first edge (D1) to an outer edge of the bonding layer (13) in the second direction is shorter than a distance from the second edge (D1) to an outer edge of the bonding layer (13) in the first direction (see figure 3, 7-8 and paragraph [0037]-[0047]).
[Re claim 2] TAJIRI discloses the semiconductor device wherein the die pad portion (211) extends across the first edge (see figure 3).
[Re claim 3] TAJIRI discloses the semiconductor device wherein the bonding layer extends across the first edge (see figure 3 and 7).
[Re claim 4] TAJIRI discloses the semiconductor device wherein the terminal portion (212) overlaps with the first edge as viewed in the thickness direction (see figure 3 and 7-8).
[Re claim 5] TAJIRI discloses the semiconductor device wherein the bonding layer (13) is in contact with the first edge (see figure 7-8).
[Re claim 7] TAJIRI discloses the semiconductor device wherein the first edge (D1) is longer than the second edge (D2) (see figure 3).
[Re claim 16] TAJIRI discloses the semiconductor device further comprising a sealing resin (50) covering a portion of the lead and the semiconductor element, wherein the sealing resin is in contact with the first edge and the second edge (see figure 3 and 7).
[Re claim 17] TAJIRI discloses the semiconductor device wherein the substrate includes a reverse surface (11B) facing away from the obverse surface (11A) in the thickness direction, and the reverse surface is exposed from the sealing resin (see figure 7).
Allowable Subject Matter
Claims 6 and 8-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817
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