DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 13, filed 12/23/2025, with respect to the objection(s) to the abstract have been fully considered and are persuasive. The associated objection(s) has been withdrawn.
Applicant’s arguments, see page 13, filed 12/23/2025, with respect to the objection(s) to the drawings have been fully considered and are persuasive. The associated objection(s) has been withdrawn.
Applicant's arguments, see pages 14-18, filed 12/23/2025, with respect to the rejection of claims 1-2,5-17 and 20-29 under 35 USC 103 have been fully considered but they are not persuasive.
Regarding the argument:
“Applicant respectfully submits that the combination of EMBEDDED.COM and Xiong fails to disclose or suggest at least claim l's recitation of "responsive to determining that the first authentication key is valid," "plac[ing] the address of the shared resource in an authenticated tagged state associated with the first requestor" (emphasis added). … While EMBEDDED.COM does mention that an addressed memory location may be flagged for exclusive access, Applicant respectfully submits that EMBEDDED.COM fails to disclose or suggest the use of any type of "authentication" involving a "first authentication key," nor does it disclose or suggest any mechanism for validating such a "first authentication key" or placing the "shared resource" in an "authenticated tagged state," as claim 1 recites (emphasis added).”
Examiner respectfully disagrees. As to teaching “the use of any type of authentication involving a first authentication key”, and “mechanism for validating such a first authentication key”, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). EMBEDDED.COM is not relied upon to teach this limitation. Instead, the prior art of XIONG is cited as explicitly teaching this limitation.
As to teaching “placing the shared resource in an authenticated tagged state”, examiner notes that prior art need not use the same terminology as a claim, as anticipation is not an ipsissimis verbis test. The function of the claimed “authenticated tagged state” is a memory location which has been identified or marked in some way. The term “authenticated” here is merely applicant’s chosen nomenclature referring to the process by which a location is chosen to be marked, and confers no function which is distinct over the flagged memory location of EMBEDDED.COM.
Regarding the argument:
“Applicant further respectfully submits that Xiong fails to provide the disclosures missing from EMBEDDED.COM in this regard. Xiong does not relate to providing mutual exclusion ("mutex") synchronization mechanisms for shared resources …. However, Xiong makes no mention of the accessed memory location being "place[d] ... in an authenticated tagged state associated with" the "remote node 402," as is the case with aspects according to claim 1.”
Examiner respectfully disagrees. As to teaching “the accessed memory location being placed in an authenticated tagged state associated with the remote node”, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). XIONG is not relied upon to teach this limitation. Instead, the prior art of EMBEDDED.COM is cited as explicitly teaching this limitation.
Regarding the argument:
“Finally, Applicant respectfully submits that the Office Action fails to provide a reasoned explanation as to why one of skill in the art would modify the disclosures of EMBEDDED.COM to incorporate the features of Xiong. … The Office Action on page 7 merely asserts that "[i]t would have been obvious ... to modify the MUTEX of EMBEDDED.COM with the authenticated data requests of XIONG with the motivation to create a system where instructions passed in a multi- processor environment are authenticated via a key included in the instructions." Applicant respectfully submits that the rationale provided by the Office Action is merely a conclusory statement that just repeats the inventive aspect of claim 1, and is insufficient to provide the required "reasoned explanation."”
Examiner respectfully disagrees. The explanation provided in the prior office action does not constitute merely a “conclusory statement” that instructions are authenticated; the entirety of the explanation goes on to explain why the references are combined; i.e. it would be obvious to look to methods which use similar keys and requests for loading and storing data. That the given motivation may be similar to that declared as an inventive aspect of the claimed invention does not make said motivation any less of a “reasoned explanation.”
Examiner notes that additional arguments are directed to assertions of allowability of dependent claims based on arguments already addressed, and will not be re-addressed here.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 15:
“means for determining whether the first authentication key is valid [function]”
“means for placing the address of the shared resource in an authenticated tagged state [function]”
“means for transmitting a return value to the first requestor [function]”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may:
amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or
present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 11, 15-17, 20, 26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs, and further in view of XIONG et al (Doc ID US 20160062944 A1).
Regarding claim 1:
EMBEDDED.COM teaches:
A processor-based device comprising: a plurality of processor cores; a shared resource communicatively coupled to each processor core of the plurality of processor cores via an interconnect (Figure 2 illustrates shared resources connected to multiple processor cores through an interconnect (bus).); and
responsive to determining that the first authentication key is valid: place the address of the shared resource in an authenticated tagged state associated with the first requestor ("LDREX – The load exclusive instruction carries out a load from an addressed memory location and also flags that location as reserved for exclusive access."); and
transmit a return value to the first requestor ("LDREX – The load exclusive instruction carries out a load from an addressed memory location ...").
EMBEDDED.COM does NOT teach:
an authenticated-exclusive monitor circuit configured to: receive, from a first requestor, an authenticated load exclusive (ALE) request that is directed to an address of the shared resource and that comprises a first authentication key;
determine whether the first authentication key is valid; and
XIONG teaches:
an authenticated-exclusive monitor circuit configured to: receive, from a first requestor, an authenticated load exclusive (ALE) request that is directed to an address of the shared resource and that comprises a first authentication key ([0037] "… an AM write request or AM read request is sent from remote node 402 to local node 400. Message 412 includes access key 408.");
determine whether the first authentication key is valid ([0037] "… Upon receipt, the AM write or AM read is validated by local node 400 using access key 408."); and
Utilizing a Mutual Exclusion (MUTEX) protocol in a multi-processor system and returning a value based on the MUTEX are known techniques in the art, as demonstrated by EMBEDDED.COM. Further, “loading” and “storing” requests which include a key used to authenticate the request are known techniques in the art, as demonstrated by XIONG. It would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify the MUTEX of EMBEDDED.COM with the authenticated data requests of XIONG with the motivation to create a system where instructions passed in a multi-processor environment are authenticated via a key included in the instructions. It would be obvious to look to systems which use a similar key to authenticate similar data loading and storing requests.
Regarding claim 2:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1, wherein the ALE request results from execution of an ALE instruction of an instruction set architecture (ISA) implemented by the processor-based device (EMBEDDED.COM "ARM provides exclusive access functionality via the LDREX/STREX pair of instructions. ").
Regarding claim 5:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1, wherein the authenticated-exclusive monitor circuit is further configured to: receive a request comprising one of: an authenticated store exclusive (ASE) request directed to the address of the shared resource from a second requestor without a lock on the address of the shared resource (EMBEDDED.COM "STREX – The store exclusive instruction ... returns a value indicating whether the addressed location was reserved for exclusive access. If it wasn’t, the store doesn’t take place ..."); and
an authenticated clear exclusive (ACLRX) request directed to the address of the shared resource from any requestor (EMBEDDED.COM "CLREX – Clear exclusive is intended for use in context switches, the CLREX instruction clears any exclusive access reservations in the memory system."); and
responsive to receiving the request, place the address of the shared resource in an untagged state (EMBEDDED.COM "The exclusive reservation is cleared regardless of whether the store succeeds or not.").
Regarding claim 11:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1, wherein: the shared resource comprises a memory device of the processor-based device (EMBEDDED.COM "LDREX – The load exclusive instruction carries out a load from an addressed memory location ..."); and
the address of the shared resource comprises a memory address indicating a memory location of the memory device (EMBEDDED.COM "LDREX – The load exclusive instruction carries out a load from an addressed memory location ...").
Regarding claims 15-17, 20, and 26:
These claims are rejected with the same justification, mutatis mutandis, as their counterpart claims 1, 2, 5, and 11 above.
Regarding claim 29:
EMBEDDED.COM teaches:
A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor-based device, cause the processor-based device to ([0042] "… Exemplary software components depicted in FIG. 5 include a host operating system 562, applications 564, and software instructions for implementing various AM handlers 566 and RMA modules 568."):
The remainder of this claim’s limitations are rejected with the same prior art mapping and justification, mutatis mutandis, as its counterpart claim 1 above.
Claims 6, 7, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs/ and XIONG et al (Doc ID US 20160062944 A1) as applied to claims 1 and 16 above, and further in view of KOTTAHACHCHI (Doc ID US 20090077645 A1).
Regarding claim 6:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1, wherein the authenticated-exclusive monitor circuit is further configured to: receive, from a third requestor, a request (XIONG [0037] "… an AM write request or AM read request is sent from remote node 402 to local node 400. Message 412 includes access key 408.");
determine whether the request comprises an authentication key (XIONG [0037] "… Upon receipt, the AM write or AM read is validated by local node 400 using access key 408."); and
responsive to determining that the request does not comprise an authentication key: transmit an authentication failure indication to the third requestor (XIONG [0037] "… an access error message 416 is returned to remote node 402 if its AM write or AM read request fails validation."); and
Determining whether a data access request includes an expected key is a known technique in the art, as demonstrated by XIONG. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the access key validation of XIONG with the motivation to validate that the expected key is present in the data access request.
The combination of EMBEDDED.COM and XIONG does NOT teach:
increment a count of failed authentication attempts by the third requestor.
KOTTAHACHCHI teaches this limitation:
[0039] "… Update step 216 ... tracks status of the last authentication attempt to "unsuccessful", increasing the count of failed authentication attempts by one,"
Incrementing a failure counter after a failed validation is a known technique in the art, as demonstrated by KOTTAHACHCHI. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the failure counter of KOTTAHACHCHI with the motivation to enable the system to allow a grace period to failed authentications so that a proper request might be sent. It is obvious to utilize a counter to prevent false positives of blocking entities after a single invalid request.
Regarding claim 7:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1, wherein the authenticated-exclusive monitor circuit is further configured to: receive, from a fourth requestor, a request comprising a second authentication key (XIONG [0037] "… an AM write request or AM read request is sent from remote node 402 to local node 400. Message 412 includes access key 408.");
determine whether the second authentication key is valid (XIONG [0037] "… Upon receipt, the AM write or AM read is validated by local node 400 using access key 408."); and
responsive to determining that the second authentication key is not valid: transmit an authentication failure indication to the fourth requestor (XIONG [0037] "… an access error message 416 is returned to remote node 402 if its AM write or AM read request fails validation."); and
Determining whether a key included in a data access request is valid is a known technique in the art, as demonstrated by XIONG. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the access key validation of XIONG with the motivation to ensure the included key is a valid key.
The combination of EMBEDDED.COM and XIONG does NOT teach:
increment a count of failed authentication attempts by the fourth requestor.
KOTTAHACHCHI teaches this limitation:
[0039] "… Update step 216 ... tracks status of the last authentication attempt to "unsuccessful", increasing the count of failed authentication attempts by one,"
Incrementing a failure counter after a failed validation is a known technique in the art, as demonstrated by KOTTAHACHCHI. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the failure counter of KOTTAHACHCHI with the motivation to enable the system to allow a grace period to failed authentications so that a proper request might be sent. It is obvious to utilize a counter to prevent false positives of blocking entities after a single invalid request.
Regarding claims 21 and 22:
These claims are rejected with the same justification, mutatis mutandis, as their counterpart claims 6 and 7 above.
Claims 8, 9, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs/ and XIONG et al (Doc ID US 20160062944 A1) as applied to claims 1 and 16 above, and further in view of GE et al (Doc ID US 20240070277 A1).
Regarding claim 8:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1,
The combination of EMBEDDED.COM and XIONG does NOT teach:
wherein: the authenticated-exclusive monitor circuit comprises an authentication circuit;
the authenticated-exclusive monitor circuit is further configured to receive, from a secure key generator, a copy of the first authentication key; and
the authenticated-exclusive monitor circuit is configured to determine whether the first authentication key is valid by being configured to, using the authentication circuit, determine whether the first authentication key matches the copy of the first authentication key.
GE teaches:
wherein: the authenticated-exclusive monitor circuit comprises an authentication circuit ([0029] "… the system(s) may then allow the machine to override the previous hashes with the new hashes that the system(s) will then use when authenticating the machine.");
Examiner notes that the broadest reasonable interpretation of an "authentication circuit" encompasses any portion of a system used to facilitate authentication.
the authenticated-exclusive monitor circuit is further configured to receive, from a secure key generator, a copy of the first authentication key ([0028] "… the system(s) may generate a key associated with the update …"); and
the authenticated-exclusive monitor circuit is configured to determine whether the first authentication key is valid by being configured to, using the authentication circuit, determine whether the first authentication key matches the copy of the first authentication key ([0029] "… the machine may send the key ... to the system(s). In either example, the system(s) may then ... comparing the received key with the generated key.").
Generating a key to use in validating an incoming access key is a known technique in the art, as demonstrated by GE. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the local key generator and key matching of GE with the motivation to use an algorithm to generate an expected key, rather than stored data of some kind, which is less secure.
Regarding claim 9:
The combination of EMBEDDED.COM, XIONG, and GE teaches:
The processor-based device of claim 8, wherein the authenticated-exclusive monitor circuit is configured to determine whether the first authentication key is valid by being further configured to, using the authentication circuit, determine whether the first authentication key is valid within a specified time interval (GE [0028] "… the key may be associated with a time window …" and [0029] "… the machine may then verify the update using the new hashes and the key, such as within the time window.").
Validating an access key within a time period is a known technique in the art, as demonstrated by GE. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM, XIONG, and GE with the timed key validation of GE with the motivation to prevent old keys from being used to validate data access requests.
Regarding claims 23 and 24:
These claims are rejected with the same justification, mutatis mutandis, as their counterpart claims 8 and 9 above.
Claims 10 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs/, XIONG et al (Doc ID US 20160062944 A1), and GE et al (Doc ID US 20240070277 A1) as applied to claims 8 and 23 above, and further in view of KOTTAHACHCHI (Doc ID US 20090077645 A1).
Regarding claim 10:
The combination of EMBEDDED.COM, XIONG, and GE teaches:
The processor-based device of claim 8,
The combination of EMBEDDED.COM, XIONG, and GE does NOT teach:
wherein the authenticated-exclusive monitor circuit is configured to determine whether the first authentication key is valid by being further configured to, using the authentication circuit, determine whether a count of failed authentication attempts by the first requestor does not exceed a failed authentication attempt threshold.
KOTTAHACHCHI teaches this limitation:
[0040] "… a policy violation may occur, for example, when a predetermined number of consecutive failed authentication attempts is reached …"
Indicating a failed validation after a threshold number of validation failures is a known technique in the art, as demonstrated by GE. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM, XIONG, and GE with the failure count threshold of GE with the motivation to block access requests from a source deemed suspicious via repeated failures to provide an expected access key.
Regarding claim 25:
This claim is rejected with the same justification, mutatis mutandis, as its counterpart claim 10 above.
Claims 12-14, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs/ and XIONG et al (Doc ID US 20160062944 A1) as applied to claims 1 and 16 above, and further in view of HORNSNELL et al (Doc ID US 20210342152 A1).
Regarding claim 12:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1,
The combination of EMBEDDED.COM and XIONG does NOT teach:
wherein: the authenticated-exclusive monitor circuit is an element of a local monitor circuit of a processor core of the plurality of processor cores; and
the first requestor comprises a thread executing on the processor core.
HORNSNELL teaches:
wherein: the authenticated-exclusive monitor circuit is an element of a local monitor circuit of a processor core of the plurality of processor cores ([0081] "… As shown in FIG. 1, this exclusive monitor indication could be held within a local exclusive monitor 30 provided within the processing element itself or within a global exclusive monitor 32 provided within the interconnect."); and
the first requestor comprises a thread executing on the processor core ([0056] "… the processing circuitry includes multiple processing elements (e.g. processor cores, CPUs or GPUs) …" and [0081] "Another way of managing locks for non-transactional threads may be to use exclusive monitors.").
Processing data access requests from a processor core utilizing a local exclusive monitor is a known technique in the art, as demonstrated by HORNSNELL. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the local exclusive monitor of HORNSNELL with the motivation to use a well-known architecture for handling mutual exclusion among threads potentially requesting access to the same registers.
Regarding claim 13:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1,
The combination of EMBEDDED.COM and XIONG does NOT teach:
wherein: the authenticated-exclusive monitor circuit is an element of a global monitor circuit of the processor-based device; and
the first requestor comprises a thread executing on a processor core of the plurality of processor cores.
HORNSNELL teaches:
wherein: the authenticated-exclusive monitor circuit is an element of a global monitor circuit of the processor-based device ([0081] "… As shown in FIG. 1, this exclusive monitor indication could be held within a local exclusive monitor 30 provided within the processing element itself or within a global exclusive monitor 32 provided within the interconnect."); and
the first requestor comprises a thread executing on a processor core of the plurality of processor cores ([0056] "… the processing circuitry includes multiple processing elements (e.g. processor cores, CPUs or GPUs) …" and [0081] "Another way of managing locks for non-transactional threads may be to use exclusive monitors.").
Processing data access requests from a processor core utilizing a global exclusive monitor is a known technique in the art, as demonstrated by HORNSNELL. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the global exclusive monitor of HORNSNELL with the motivation to use a well-known architecture for handling mutual exclusion among threads potentially requesting access to the same registers.
Regarding claim 14:
The combination of EMBEDDED.COM and XIONG teaches:
The processor-based device of claim 1,
The combination of EMBEDDED.COM and XIONG does NOT teach:
integrated into a device selected from the group consisting of: … a computer; a portable computer; a mobile computing device …”
HORNSNELL teaches this limitation:
[0006] "... examples provide an apparatus comprising:", and [0007] "processing circuitry to process threads of data processing; and", and [0008] "transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry ..."
Integrating a multi-core processor into a device is a known technique in the art, as demonstrated by HORNSNELL. It would have been obvious to a PHOSITA before the effective filing date of the claimed invention to modify the authenticated MUTEX of EMBEDDED.COM and XIONG with the integrated device of HORNSNELL with the motivation to incorporate the authenticated MUTEX into a device capable of performing some function.
Regarding claims 27 and 28:
These claims are rejected with the same justification, mutatis mutandis, as their counterpart claims 12 and 13 above.
Allowable Subject Matter
Claims 3, 4, 18, 19, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3:
XIONG et al (Doc ID US 20160062944 A1) teaches the following limitations:
The processor-based device of claim 1, wherein the authenticated-exclusive monitor circuit is further configured to: subsequently receive, from the first requestor, an authenticated store exclusive (ASE) request that is directed to the address of the shared resource and that comprises the first authentication key ([0037] "… an AM write request or AM read request is sent from remote node 402 to local node 400. Message 412 includes access key 408.");
determine whether the first authentication key is valid ([0037] "… Upon receipt, the AM write or AM read is validated by local node 400 using access key 408."); and
The website at https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs teaches the following limitation:
responsive to determining that the first authentication key is valid: determine whether the address of the shared resource is in the authenticated tagged state associated with the first requestor ("STREX – The store exclusive instruction stores from a register to an addressed memory location and returns a value indicating whether the addressed location was reserved for exclusive access."); and
The following limitations are novel and are not taught by XIONG or EMBEDDED.COM alone or in combination:
responsive to determining that the address of the shared resource is in the authenticated tagged state associated with the first requestor: acquire a lock on the address of the shared resource for the first requestor; and
subsequent to a store operation using the address of the shared resource, place the address of the shared resource in an untagged state.
Regarding claims 18 and 30:
These claims are allowable with the same justification, mutatis mutandis, as their counterpart claim 3.
Regarding claims 4 and 19:
These claims are dependent on one or more allowed claims, and are thus allowable.
Regarding claim 4:
The website at https://www.embedded.com/dealing-with-memory-access-ordering-in-complex-embedded-designs is of note for teaching the following:
The processor-based device of claim 3, wherein the ASE request results from execution of an ASE instruction of an instruction set architecture (ISA) implemented by the processor-based device ("ARM provides exclusive access functionality via the LDREX/STREX pair of instructions.").
Regarding claim 19:
This claim is mapped to prior art in the same manner as its counterpart claim 4.
It should be noted that the determination of allowability is made on the combination of all limitations/features recited in the independent claims and not a single limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BB/Examiner, Art Unit 2437
/BENJAMIN E LANIER/Primary Examiner, Art Unit 2437