Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This final Office action is responsive to Applicants’ response filed on 03/10/2026. Claims 1-20 are presented for examination and are rejected for the reasons indicated herein below.
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Inoue et al. (U.S. Pub. No. 2006/0006850 A1) in view of Morita (U.S. Pub. No. 2002/0118553 A1).
Regarding claim 1, Inoue et al. (e.g. see Figs. 1-21) discloses “A power converter configured to receive an input voltage (e.g. Figs. 1-5 and 12-13, see input Vi), and the power converter comprising: a boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see 3), a bypass switch connected between the boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see 3 and 5. Implicit), and a comparison circuit configured to receive the input voltage and a voltage threshold, and compare the input voltage with the voltage threshold to generate a first control signal and a second control signal (e.g. Figs. 1-5 and 12-13, see Vi, 7, 7A, 7B and 6 and the output of 7 and 6, also see para. 0161-0168 and para. 0238-0248. Implicit), wherein when the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch (5) and the second control signal disables the boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see Vi, 3, 5, 7, 7A, 7B and 6 and the output of 7 and 6, also see para. 0161-0168 and para. 0238-0248. Implicit)”. Inoue et al. does not appear to explicitly disclose “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage”. However, Morita shows “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage (Morita, e.g. Fig. 3, see 40)”. Having a DC-to-DC conversion circuit connected to a boost power factor correction circuit as taught by Morita in the power converter of Inoue et al. would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a DC-to-DC conversion circuit connected to a boost power factor correction circuit as taught by Morita in the power converter of Inoue et al. for the purpose of enabling the power converter of Inoue et al. to be used with other types of converters such as DC-DC converters to convert DC voltage to DC output to be used for DC loads. Also for the purpose of making the device more widely usable.
Regarding claim 2, the combination of Inoue et al. (e.g. see Figs. 1-21) and Morita (e.g. see Fig. 3) discloses “wherein when the input voltage is less than the voltage threshold, the first control signal turns off the bypass switch (5) and the second control signal enables the boost power factor correction circuit (3) so that the boost power factor correction circuit performs a power factor correction to the input voltage to generate a conversion voltage, and the conversion voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the conversion voltage into the output voltage (e.g. Figs. 1-5 and 12-13, see Vi, 3, 5, 7, 7A, 7B and 6 and the output of 7 and 6, also see para. 0161-0168 and para. 0238-0248, also see Morita, e.g. Fig. 3, see 40. Implicit)”.
Regarding claim 3, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the boost power factor correction circuit comprises: an inductor (3L) comprising a first terminal and a second terminal (e.g. Figs. 1-5 and 12-13, see 3L and its connections. Implicit); the first terminal of the inductor (L3) configured to receive the input voltage (Vi), a diode (3D) comprising an anode and a cathode (e.g. Figs. 1-5 and 12-13, see 3L and 3D and their connections. Implicit); the anode connected to the second terminal of the inductor (e.g. Figs. 1-5 and 12-13, see 3L and 3D and their connections. Implicit), and a switch (3S) comprising a first terminal, a second terminal, and a control terminal (e.g. Figs. 1-5 and 12-13, see 3S and its terminals. Implicit); the first terminal of the switch connected to the anode of the diode, and the second terminal of the switch is grounded (e.g. Figs. 1-5 and 12-13, see 3L, 3S and 3D and their connections. Implicit)”.
Regarding claim 4, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the second control signal is configured to control the switch (3S) to disable or enable the boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see 7, 4, 3 and 3S and their connections. Implicit)”.
Regarding claim 5, Inoue et al. (e.g. see Figs. 1-21) discloses “further comprising: a switch controller (4C) connected to the control terminal of the switch (3S), and configured to generate a switch control signal (SG) to control the turning on and turning off of the switch (e.g. Figs. 1-5 and 12-13, see 7, 4, 4C, 3, SG and 3S. Implicit)”.
Regarding claim 6, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the second control signal is configured to control the switch controller (4C) to disable or enable the boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see 7, 4, 4C, 3, SG and 3S. Implicit)”.
Regarding claim 7, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the bypass switch (5) is connected between the first terminal of the inductor (3L) and the cathode of the diode (e.g. Figs. 1-5 and 12-13, see 5, 3L and 3D and their connections. Implicit)”.
Regarding claim 8, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the bypass switch (5) comprises a first terminal, a second terminal, and a control terminal (e.g. Figs. 1-5 and 12-13, see 5 and its connections. Implicit); the first terminal of the bypass switch (5) is connected to the first terminal of the inductor (3L), and the second terminal of the bypass switch is connected to the cathode of the diode (e.g. Figs. 1-5 and 12-13, see 5, 3L and 3D and their connections. Implicit)”.
Regarding claim 9, Inoue et al. (e.g. see Figs. 1-21) discloses “wherein the first control signal is configured to control the turning on and turning off of the bypass switch (e.g. Figs. 1-5 and 12-13, see Vi, 5, 7, 7A, 7B and 6 and the output of 7 and 6, also see para. 0161-0168 and para. 0238-0248. Implicit)”.
Regarding claim 10, Inoue et al. (e.g. see Figs. 1-21) discloses “further comprising: a capacitor (3C) comprising a first terminal and a second terminal (e.g. Figs. 1-5 and 12-13, see 3C and its connections); the first terminal of the capacitor is configured to receive the input voltage or the conversion voltage (e.g. Figs. 1-5 and 12-13, see Vi, 3C and its connections. Implicit)”.
Regarding method claims 11-20; they all comprise substantially same subject matter as in the recited apparatus claims 1-10, therefore method claims 11-20 are also rejected under the same ground of rejection as clearly discussed in the rejection to the apparatus claims 1-10. Also the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated).
Response to Argument(s)
3. Applicant's argument(s) filed on 03/10/2026 have been fully considered but they are not persuasive and also the claims submitted on 03/10/2026 are also still rejected in view of the same grounds of rejection.
In the remarks,
Applicant argues in the response that:
The combination of Inoue et al. and Morita does not disclose the features of “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, and a comparison circuit configured to receive the input voltage and a voltage threshold, and compare the input voltage with the voltage threshold to generate a first control signal and a second control signal, wherein when the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch and the second control signal disables the boost power factor correction circuit so that the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage” as recited in Applicant’s claim 1 and similarly in claim 11.
In response to argument(s):
Examiner respectfully disagrees. Applicant is reminded that claims must be given their broadest reasonable interpretation.
Also in response to applicant's arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Also, it is respectfully requested that, in preparing responses, the applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Likewise, in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Similarly, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Moreover, in response to applicant's argument that none of the above-mentioned references disclose the above-mentioned limitations, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Therefore, the combination of Inoue et al. and Morita clearly discloses all the claimed limitations based on the broadest reasonable interpretation. The limitations “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, and a comparison circuit configured to receive the input voltage and a voltage threshold, and compare the input voltage with the voltage threshold to generate a first control signal and a second control signal, wherein when the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch and the second control signal disables the boost power factor correction circuit so that the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage”, as recited in Applicant's claim 1 and similarly in claim 11, are in fact still read on the combination of Inoue et al. and Morita for example, (Inoue et al. shows “a comparison circuit configured to receive the input voltage and a voltage threshold, and compare the input voltage with the voltage threshold to generate a first control signal and a second control signal (e.g. Figs. 1-5 and 12-13, see Vi, 7, 7A, 7B and the output of 7, also see para. 0161-0168 and para. 0237-0248. Examiner’s note: Applicant used only Fig. 4 for their arguments, where Examiner pointed out to more than one figure in the prior art. At least Fig. 12 indeed discloses the comparison circuit which is configured to receive the input voltage and a voltage threshold, and compare the input voltage with the voltage threshold to generate a first control signal and a second control signal. It is therefore respectfully requested that, in preparing responses, the applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Implicit), wherein when the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch (5) and the second control signal disables the boost power factor correction circuit (e.g. Figs. 1-5 and 12-13, see Vi, 3, 5, 7, 7A, 7B and the output of 7, also see para. 0161-0168 and para. 0237-0248. Examiner’s note: Applicant used only Fig. 4 for their argument, where Examiner pointed out to more than one figure in the prior art. At least Fig. 12 indeed discloses wherein when the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch (5) and the second control signal disables the boost power factor correction circuit. It is therefore respectfully requested that, in preparing responses, the applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Implicit))”.
Inoue et al. does not appear to explicitly disclose “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage”. However, Morita shows “a DC-to-DC conversion circuit connected to the boost power factor correction circuit, the input voltage is provided to the DC-to-DC conversion circuit and the DC-to-DC conversion circuit converts the input voltage into an output voltage (Morita, e.g. Fig. 3, see 40)”. Having a DC-to-DC conversion circuit connected to a boost power factor correction circuit as taught by Morita in the power converter of Inoue et al. would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a DC-to-DC conversion circuit connected to a boost power factor correction circuit as taught by Morita in the power converter of Inoue et al. for the purpose of enabling the power converter of Inoue et al. to be used with other types of converters such as DC-DC converters in order to convert DC voltage to DC output to be used for DC loads. Also for the purpose of making the device more widely usable
To clarify this further, the combination of Inoue et al. and Morita indeed teaches the argued limitations. Inoue et al. teaches the PFC circuit, the bypass switch and the comparison circuit but doesn’t teach the DC-DC conversion circuit at the output of the PFC circuit. Morita indeed teaches the DC-DC conversion circuit at the output of the PFC circuit. Again, as discussed in the rejection above of independent claim 1, and similarly independent claim 11, the combination of Inoue et al. and Morita clearly shows these limitations (see the rejection and response to arguments above). Thus, applicant's arguments are invalid.
Conclusion
4. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Relevant References:
(Chang et al. (U.S. Pub. No. 2010/0014330 A1; e.g. see Figs. 1-3)).
(Hung et al. (U.S. Pub. No. 2017/0329380 A1; e.g. see Figs. 2-7)).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUSEF A AHMED whose telephone number is (571)272-6057. The examiner can normally be reached on Monday-Friday 11AM-7PM.
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/YUSEF A AHMED/Primary Examiner, Art Unit 2838