DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120) and Liu et al. (US 2013/0182505).
In regards to claims 1, 8, and 15, Cho teaches a memory device comprising:
a memory array (memory cell array 1100, figure 1); and
control logic (control logic 1500, figure 1), operatively coupled with the memory array, configured to perform operations comprising:
identifying a request to execute a programming operation to program a plurality of sub-blocks comprising a first sub-block and a second sub-block of a memory device (“The memory 1522 may be used to store not only data (for example, 1-page data) to be stored in memory cells connected with one word line, but also data (for example, plural page data) to be stored in memory cells connected with commonly connected word lines (for example, WLi1 to WLi4) of the same word line layer. In case of the non-volatile memory device according to an exemplary embodiment of the inventive concept, at a program operation, the memory 1522 may store data (for example, plural page data) to be stored in memory cells connected with commonly connected word lines (for example, WLi1 to WLi4) of the same word line layer.”, paragraph 0068);
executing a first drive operation to load first data into a first pillar associated with the first sub-block (“First of all, in operation S100, memory cells of electrically connected word lines WL11 to WL14 may be programmed simultaneously to the first state (for example, a `01` state in FIG. 5).”, paragraph 0083; “Each string 1101 is connected to a corresponding bit line via a corresponding string selection transistor and to a common source line CSL via a corresponding ground selection transistor. For example, a string 1101 is connected to a bit line BL0 via a string selection transistor controlled by a corresponding one SSL00 of a group of string selection lines SSL00 to SSL03, and to the common source line CSL via a ground selection transistor controlled by a ground selection line GSL0.”, paragraph 0063; “With an embodiment for a non-volatile memory device, the upper wires 270 are used as bit lines connected to one ends of cell strings.”, paragraph 0169; See figure 43); and
executing one or more program bias disturb mitigation operations during execution of a second drive operation to apply a second drive pulse to load second data into a second pillar associated with the second sub-block (“In particular, at each program loop, all or a part of string selection lines of each string selection line group may be activated at the same time.”, paragraph 0067; “If a program operation on the first state (a `01` state) is determined to be completed in operation S110, the procedure goes to operation S140, in which memory cells of the electrically connected word lines WL11 to WL14 may be programmed to the second state (for example, a `00` state in FIG. 5) at the same time.”, paragraph 0089; “Each string 1101 is connected to a corresponding bit line via a corresponding string selection transistor and to a common source line CSL via a corresponding ground selection transistor. For example, a string 1101 is connected to a bit line BL0 via a string selection transistor controlled by a corresponding one SSL00 of a group of string selection lines SSL00 to SSL03, and to the common source line CSL via a ground selection transistor controlled by a ground selection line GSL0.”, paragraph 0063).
Cho fails to adequately teach apply the first drive pulse to the first select gate drain (SGD) to load first data;
apply the second drive pulse to a second SGD to load second data; and
wherein the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block.
Park teaches that the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block (“A plurality of pages, including at least two pages pertaining to the same memory plane, can be simultaneously programmed”, abstract) “thereby reducing a program time” (paragraph 0103). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park such that the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block “thereby reducing a program time” (id.).
Cho in view of Park fails to adequately teach apply the first drive pulse to the first select gate drain (SGD) to load first data; and
apply the second drive pulse to a second SGD to load second data.
Liu teaches apply the first drive pulse to the first select gate drain (SGD) to load first data (“During the first phase, a sequence of pulses is applied using a bias arrangement like that of a typical ISPP, where the bit line is maintained at about ground potential, the SSL line is driven to about VCC, the word lines for unselected cells are driven to a pass voltage level, and the word line for the selected cell is driven to a program potential. FIG. 9 shows three program bias pulses in the first phase, including pulse 200, pulse 201 and pulse 202.”, paragraph 0063); and
apply the second drive pulse to a second SGD to load second data (“During the first phase, a sequence of pulses is applied using a bias arrangement like that of a typical ISPP, where the bit line is maintained at about ground potential, the SSL line is driven to about VCC, the word lines for unselected cells are driven to a pass voltage level, and the word line for the selected cell is driven to a program potential. FIG. 9 shows three program bias pulses in the first phase, including pulse 200, pulse 201 and pulse 202.”, paragraph 0063)
to prevent disturbance due to GIDL-induced leakage (paragraph 0108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park and Liu to include apply the first drive pulse to the first select gate drain (SGD) to load first data; and
apply the second drive pulse to a second SGD to load second data
to prevent disturbance due to GIDL-induced leakage (id.).
In regards to claims 2, 9, and 16, Liu further teaches that the one or more program bias disturb mitigation operations comprise applying a ramped voltage to the second SGD during the second drive operation (“The SSL voltage V-SSL is about VCC during the initial portion, and decreased slightly during a subsequent portion of the pulse.”, paragraph 0064; See also figure 9).
In regards to claims 3 and 10, Cho further teaches that he one or more program bias disturb mitigation operations comprise programming a portion of at least one of the first sub-block or the second sub-block (“In particular, at each program loop, all or a part of string selection lines of each string selection line group may be activated at the same time.”, paragraph 0067).
In regards to claims 7, 14, and 17, Liu further teaches that the one or more program bias disturb mitigation operations comprise increasing a program bias voltage associated with one or more of the first SGD or the second SGD (“Also, the program voltage during pulse 303 is increased to a first level 311 during an initial part of the pulse, and then boosted to a level 311' during a subsequent portion of the pulse.”, paragraph 0069).
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120), Liu et al. (US 2013/0182505), and Ameen et al. (US 2023/0352092).
In regards to claims 4, 11, and 18, Cho in view of Park and Liu teaches claims 1, 8, and 15. Cho in view of Park and Liu fails to teach that the one or more program bias disturb mitigation operations comprise executing a staggered discharge of a program bias voltage associated with the second SGD. Ameen teaches that the one or more program bias disturb mitigation operations comprise executing a staggered discharge of a program bias voltage associated with the second SGD (“Then, a rigorous stagger discharge of the array 10 is done by taking the potential of one bundle of word lines after another to the ground, causing a waterfall of electrons exiting the pillars.”, paragraph 0019) in order to lower the word line potential (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Liu, and Ameen such that the one or more program bias disturb mitigation operations comprise executing a staggered discharge of a program bias voltage associated with the second SGD in order to lower the word line potential (id.).
Claims 5, 6, 12, 13, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120), Liu et al. (US 2013/0182505), and Hung et al. (US 2007/0014157).
In regards to claims 5, 12, and 19, Cho in view of Park and Liu teaches claims 1, 8, and 15. Cho in view of Park and Liu fails to teach that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD. Hung teaches that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD (“A current limiting circuit 118 is coupled between array source line 116 and a voltage reference such as ground.”, paragraph 0024) which “limits the magnitude of that leakage current” (paragraph 0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Liu, and Hung such that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD which “limits the magnitude of that leakage current” (id.).
In regards to claims 6 and 13, Cho in view of Park and Liu teaches claims 1 and 8. Cho in view of Park and Liu fails to teach that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation. Hung teaches that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation (“Selected cell 202-L00 is programmed by applying higher bias voltages to block select line 212, word line WL(0), and bit line BL(0), and applying lower bias voltages to block select line 214, nonselected word lines WL(1)-WL(n), and nonselected bit lines BL(1)-BL(m).”, paragraph 0025) in order “to facilitate electron injection in selected cell” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Liu, and Hung such that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation in order “to facilitate electron injection in selected cell” (id.).
In regards to claim 20, Cho in view of Park and Liu teaches claim 15. Cho in view of Park and Liu fails to teach that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation. Hung teaches that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation (“Selected cell 202-L00 is programmed by applying higher bias voltages to block select line 212, word line WL(0), and bit line BL(0), and applying lower bias voltages to block select line 214, nonselected word lines WL(1)-WL(n), and nonselected bit lines BL(1)-BL(m).”, paragraph 0025) in order “to facilitate electron injection in selected cell” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Liu, and Hung such that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation in order “to facilitate electron injection in selected cell” (id.).
Response to Arguments
Applicant’s arguments, see pages 8-9, filed 25 June 2026, with respect to the drawing objection have been fully considered and are persuasive. The drawing objection has been withdrawn.
Applicant’s arguments, see pages 9-11, filed 25 June 2026, with respect to the obviousness rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 4 August 2026
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