DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 January 2026 has been entered.
Drawings
The drawings are objected to because paragraphs 0050-0053 and 0055 use different reference numbers than figure 1B does. The specification refers to array of memory cells 104 and I/O control circuitry 160, while figure 1B shows array of memory cells 150 and I/O control circuitry 112. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, concurrently programming the first and second sub-blocks must be shown or the feature canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 8, 10, 11, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120) and Ameen et al. (US 2023/0352092).
In regards to claims 1, 8, and 15, Cho teaches a memory device comprising:
a memory array (memory cell array 1100, figure 1); and
control logic (control logic 1500, figure 1), operatively coupled with the memory array, configured to perform operations comprising:
identifying a request to execute a programming operation to program a plurality of sub-blocks comprising a first sub-block and a second sub-block of a memory device (“The memory 1522 may be used to store not only data (for example, 1-page data) to be stored in memory cells connected with one word line, but also data (for example, plural page data) to be stored in memory cells connected with commonly connected word lines (for example, WLi1 to WLi4) of the same word line layer. In case of the non-volatile memory device according to an exemplary embodiment of the inventive concept, at a program operation, the memory 1522 may store data (for example, plural page data) to be stored in memory cells connected with commonly connected word lines (for example, WLi1 to WLi4) of the same word line layer.”, paragraph 0068);
executing a first drive operation to a first select gate drain (SGD) associated with programming the first sub-block into the first SGD (“First of all, in operation S100, memory cells of electrically connected word lines WL11 to WL14 may be programmed simultaneously to the first state (for example, a `01` state in FIG. 5).”, paragraph 0083; “Each string 1101 is connected to a corresponding bit line via a corresponding string selection transistor and to a common source line CSL via a corresponding ground selection transistor. For example, a string 1101 is connected to a bit line BL0 via a string selection transistor controlled by a corresponding one SSL00 of a group of string selection lines SSL00 to SSL03, and to the common source line CSL via a ground selection transistor controlled by a ground selection line GSL0.”, paragraph 0063); and
executing one or more program bias disturb mitigation operations during execution of a second drive operation to a second SGD to load second data associated with programming the second sub-block into the second SGD (“In particular, at each program loop, all or a part of string selection lines of each string selection line group may be activated at the same time.”, paragraph 0067; “If a program operation on the first state (a `01` state) is determined to be completed in operation S110, the procedure goes to operation S140, in which memory cells of the electrically connected word lines WL11 to WL14 may be programmed to the second state (for example, a `00` state in FIG. 5) at the same time.”, paragraph 0089; “Each string 1101 is connected to a corresponding bit line via a corresponding string selection transistor and to a common source line CSL via a corresponding ground selection transistor. For example, a string 1101 is connected to a bit line BL0 via a string selection transistor controlled by a corresponding one SSL00 of a group of string selection lines SSL00 to SSL03, and to the common source line CSL via a ground selection transistor controlled by a ground selection line GSL0.”, paragraph 0063).
Cho fails to adequately teach executing the first drive operation to apply a first drive pulse to the first select gate drain;
executing the second drive operation to apply a second drive pulse to the second SGD; and
that the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block.
Park teaches that the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block (“A plurality of pages, including at least two pages pertaining to the same memory plane, can be simultaneously programmed”, abstract) “thereby reducing a program time” (paragraph 0103). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park such that the first drive operation and the second drive operation are executed during the programming operation to concurrently program the first sub-block and the second sub-block “thereby reducing a program time” (id.).
Cho in view of Park fails to adequately teach executing the first drive operation to apply a first drive pulse to the first select gate drain; and
executing the second drive operation to apply a second drive pulse to the second SGD.
Ameen teaches executing the first drive operation to apply a first drive pulse to the first select gate drain (“For example, programing the desired different levels of various the cells in the page 18 involves issuing a series of programing pulses that are applied to the selected (‘Sel’) word line to inject electrons in the charge storage (e.g., trap/floating gate, etc.).”, paragraph 0015; “A page 18 is the programmable unit of the array 10 and is accessible within a block by selecting a word line, a drain-side select gate (SGD, e.g., ‘SGD15’), and a source-side select gate (SGS, e.g., ‘SGS3’).”, paragraph 0014); and
executing the second drive operation to apply a second drive pulse to the second SGD (“For example, programing the desired different levels of various the cells in the page 18 involves issuing a series of programing pulses that are applied to the selected (‘Sel’) word line to inject electrons in the charge storage (e.g., trap/floating gate, etc.).”, paragraph 0015; “A page 18 is the programmable unit of the array 10 and is accessible within a block by selecting a word line, a drain-side select gate (SGD, e.g., ‘SGD15’), and a source-side select gate (SGS, e.g., ‘SGS3’).”, paragraph 0014)
in order “to inject electrons in the charge storage” (paragraph 0015).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park and Ameen to include executing the first drive operation to apply a first drive pulse to the first select gate drain; and
executing the second drive operation to apply a second drive pulse to the second SGD
in order “to inject electrons in the charge storage” (id.).
In regards to claims 3 and 10, Cho further teaches that he one or more program bias disturb mitigation operations comprise programming a portion of at least one of the first sub-block or the second sub-block (“In particular, at each program loop, all or a part of string selection lines of each string selection line group may be activated at the same time.”, paragraph 0067).
In regards to claims 4, 11, and 18, Ameen further teaches that the one or more program bias disturb mitigation operations comprise executing a staggered discharge of a program bias voltage associated with the second SGD (“Then, a rigorous stagger discharge of the array 10 is done by taking the potential of one bundle of word lines after another to the ground, causing a waterfall of electrons exiting the pillars.”, paragraph 0019).
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120), Ameen et al. (US 2023/0352092), and Chae et al. (US 2006/0133149).
In regards to claims 2, 9, and 16, Cho in view of Park and Ameen teaches claims 1, 8, and 15. Cho in view of Park and Ameen fails to teach that the one or more program bias disturb mitigation operations comprise applying a ramped voltage to the second SGD during the second drive operation. Chae teaches that the one or more program bias disturb mitigation operations comprise applying a ramped voltage to the second SGD during the second drive operation (“FIG. 4 is a graph showing an output waveform of a ramping voltage (VpgmR) generated in successive program cycles by a ramping circuit 50.”, paragraph 0078) in order to reduce coupling noise (paragraph 0077). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Ameen, and Chae such that the one or more program bias disturb mitigation operations comprise applying a ramped voltage to the second SGD during the second drive operation in order to reduce coupling noise (id.).
Claims 5-7, 12-14, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0310673) in view of Park et al. (US 2008/0101120), Ameen et al. (US 2023/0352092), and Hung et al. (US 2007/0014157).
In regards to claims 5, 12, and 19, Cho in view of Park and Ameen teaches claims 1, 8, and 15. Cho in view of Park and Ameen fails to teach that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD. Hung teaches that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD (“A current limiting circuit 118 is coupled between array source line 116 and a voltage reference such as ground.”, paragraph 0024) which “limits the magnitude of that leakage current” (paragraph 0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park and Hung such that the one or more program bias disturb mitigation operations comprise executing a current-limited discharge of a program bias voltage associated with the second SGD which “limits the magnitude of that leakage current” (id.).
In regards to claims 6 and 13, Cho in view of Park and Ameen teaches claims 1 and 8. Cho in view of Park and Ameen fails to teach that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation. Hung teaches that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation (“Selected cell 202-L00 is programmed by applying higher bias voltages to block select line 212, word line WL(0), and bit line BL(0), and applying lower bias voltages to block select line 214, nonselected word lines WL(1)-WL(n), and nonselected bit lines BL(1)-BL(m).”, paragraph 0025) in order “to facilitate electron injection in selected cell” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Ameen, and Hung such that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation in order “to facilitate electron injection in selected cell” (id.).
In regards to claims 7, 14, and 17, Cho in view of Park and Ameen teaches claims 1, 8, and 15. Cho in view of Park and Ameen fails to teach that the one or more program bias disturb mitigation operations comprise increasing a program bias voltage associated with one or more of the first SGD or the second SGD. Hung teaches that the one or more program bias disturb mitigation operations comprise increasing a program bias voltage associated with one or more of the first SGD or the second SGD (“Selected cell 202-L00 is programmed by applying higher bias voltages to block select line 212, word line WL(0), and bit line BL(0), and applying lower bias voltages to block select line 214, nonselected word lines WL(1)-WL(n), and nonselected bit lines BL(1)-BL(m).”, paragraph 0025) in order “to facilitate electron injection in selected cell” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Ameen, and Hung such that the one or more program bias disturb mitigation operations comprise increasing a program bias voltage associated with one or more of the first SGD or the second SGD in order “to facilitate electron injection in selected cell” (id.).
In regards to claim 20, Cho in view of Park and Ameen teaches claim 15. Cho in view of Park and Ameen fails to teach that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation. Hung teaches that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation (“Selected cell 202-L00 is programmed by applying higher bias voltages to block select line 212, word line WL(0), and bit line BL(0), and applying lower bias voltages to block select line 214, nonselected word lines WL(1)-WL(n), and nonselected bit lines BL(1)-BL(m).”, paragraph 0025) in order “to facilitate electron injection in selected cell” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho with Park, Ameen, and Hung such that the one or more program bias disturb mitigation operations comprise reducing a program bias voltage associated with one or more of the first SGD or a select gate source (SGS) associated with the first sub-block during the second drive operation in order “to facilitate electron injection in selected cell” (id.).
Response to Arguments
Applicant's arguments, see pages 6-7, filed 15 January 2026, with respect to the drawing objections have been fully considered, but they are not persuasive. No additional replacement drawing sheets have been submitted since the final rejection.
Applicant's arguments, see pages 7-10, filed 15 January 2026, with respect to the prior art rejections have been fully considered but they are either not persuasive or are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for those particular teachings specifically challenged in the argument.
Cho's drive operation does load data into different SGD's for different sub-blocks. Cho teaches programming memory cells connected to word lines WL11 to Wl14 simultaneously (paragraph 0083). Figure 2 of Cho shows that WL11 to WL14 use different transistors connected different string select line groups, which are the different claimed select gate drains.
The Examiner is interpreting Cho's teaching of only activating a part of string selection lines of each string selection group (paragraph 0067) as teaching the claimed program bias disturb mitigation operation because the cells connected to those string selection lines not activated will experience less program bias disturb because they will not be on an activated string.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 6 April 2026
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