Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are presented in the case.
Information Disclosure Statement
The information disclosure statement submitted on 03/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, 9, 13, 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3 and 13, the phrase “wherein the graph G′ does not include any disconnected qubits.” There is insufficient antecedent basis for this limitation in the claim. Qubits are not yet established in claim 3. Qubits are established in claim 2 but claim 3 depends on claim 1 currently.
Regarding claim 4 and 14, the phrase “wherein qubits identified in the graph G′ are a minimum number of qubits” There is insufficient antecedent basis for this limitation in the claim. Qubits are not yet established in claim 4. Where is the identifying qubits step?
Regarding claim 9 and 19, the phrase “an adjacency degree equal to one should be removed” “Should” is an unclear relative term. Is removal mandatory or preferred/advisory?
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (“2019 PEG”)
Claims 1 and 11 have the following abstract idea analysis.
Step 1: The claims are directed to “a method and CRM. The claims are directed to the statutory categories accordingly.
Step 2A Prong 1: claim recites the abstract idea limitations of "ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R" and "identifying nodes and edges in the graph G′;". The limitations include a mathematical concept see MPEP § 2106.04(a)(2)) where it cites textual recitation can still be mathematical "determining a ration of A to B". The specification also provides example math using Fourier and cosine functions (See USPGPUB ¶3 and ¶18). See USPTO 2024 example 48 where STFT conversion and determining vectors by formula were treated as mathematical operations. Thus, the limitations are an abstract idea in the “mathematical concept”. Other sections of the claims such as "hardware processors" "graph G", "an adjacency criterion" and "storage medium" are advanced processes, too generic or high level to be listed as a judicial exception given the available descriptions and MPEP comparisons.
Step 2A Prong 2: The judicial exceptions recited in these claims are not integrated into a practical application. Merely invoking "hardware processors" "graph G", "an adjacency criterion" and "storage medium" does not yield eligibility. Claims are still in line with mathematical concepts such as claims 1 and 11 are not specific to a practical application. The additional elements as such are processors and instructions which do not include specialized hardware. See MPEP § 2106.05(a). The math is just being used to produce a result. Claims 1 and 11 do not include a more specific field but even doing so may not be sufficient to overcome the abstract idea rejection. Merely applying an math to a field without an advancement in the new field or new hardware is ineligible. See MPEP § 2106.05(h).
Step 2B: The claims do not contain significantly more than their judicial exceptions. Processors, memory and other hardware are in their standard forms in the field. Note generic processors are recited not new quantum processors. These additional elements are well-understood, routine, and conventional activity, see MPEP 2106.05(d)(II). Claims lacks any particular "how" or algorithm for a solution in a field in a novel way. Claims require more specificity on processes that would be incapable of simple mathematics, mental processes or use more substantial structure than conventional devices such as non-textbook implementations.
Regarding claims 2-10 and 12-20 they merely narrow the previously recited abstract idea limitations with more abstract concepts and/or routine fundamental processes. For the reasons described above with respect to claim 1 and 11 this judicial exception is not meaningfully integrated into a practical application, or significantly more than the abstract idea. Abstract idea steps 1, 2A prong 1 and 2 remain the same as independent analysis above. See specification for more practical application concepts as none are seen in claims 2-10 and 12-20.
With respect to step 2B These claims disclose similar limitations described for the dependent claims above and do not provide anything significantly more than organizing human activity concepts. Claims 2-10 and 12-20 recite the additional elements of "wherein the graph G′ maps the nodes to qubits implemented in hardware. wherein the graph G′ does not include any disconnected qubits. wherein qubits identified in the graph G′ are a minimum number of qubits needed in a real quantum annealer to solve a quadratic unconstrained binary optimization problem. wherein the edges e are ranked according to their respective connection coefficient. wherein the graph G′ has fewer edges than the graph G. wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain. wherein the adjacency criterion specifies that an edge that has at least one node with an adjacency degree equal to one should be removed from the graph G′. wherein the nodes and edges are identified using Tarjan's algorithm.". These elements are more abstract concepts, generic applications to a field of use or well-understood, routine, conventional activity (see MPEP § 2106.05(d) and can't be simply appended to qualify as significantly more or being a practical application. What type of application, or structure of components beyond generic machine learning is still unknown for these claims. Therefore claims 2-10 and 12-20 also recites abstract ideas that do not integrate into a practical application or amount to significantly more than the judicial exception, and are rejected under U.S.C. 101.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9, 11-14, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over DUDASH et al. (US 20230325461 A1) hereinafter Dudash in view of ADACHI et al. (US 20160055421 A1) hereinafter Adachi and Coury et al. (US 20110238607 A1) hereinafter Coury.
As to independent claim 1, Dudash teaches a method, comprising:
creating a graph G′ by copying G; and [Dudash created a candidate local graph via copying ¶6 "copying the best local current graph to form a best local current graph copy, modifying the best local current graph copy to form a candidate local graph"]
for each of the edges e, performing, for as long as a stop criterion has not been met, operations comprising: [Dudash iterates graph until convergence (stop criterion) ¶95 " rather than using a fixed iteration number t, the system may instead apply one or more convergence conditions to determine when iterations should stop"]
identifying nodes and edges in the graph G′; [defines and identifies the graph with vertices (nodes) and edges ¶22, ¶75 "An undirected graph may be defined by a plurality of vertices (or nodes) and a plurality of edges that link respective pairs of vertices to one another"]
Dudash does not specifically teach ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R.
However, Adachi teaches ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R; [Adachi ordered (ranked) list of edges via graph embedding ¶84 "graph embedding technique"…"The list of all edges may be ordered or random"], [minor embedding ¶5]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the graph embedding disclosed by Dudash by incorporating the ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R disclosed by Adachi because both techniques address the same field of quantum computing and by incorporating Adachi into Dudash provides a better implement computationally efficient heuristic schemes that may be capable of operationally executing complex graph embedding into a particular quantum device [Adachi ¶8]
Dudash and Adachi do not specifically teach removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; removing, from the list R, all edges of the set B′ of edges; and removing, from the graph G′, the edge e.
However, Coury teaches removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; [prunes vertex with edges according to adjacency and moves them (places them into an intra-island edge set (B)) ¶37-38, ¶59, ¶48 "performing a degree-K pruning, wherein K is a positive integer; disconnecting at least one vertex from at least one island; connecting at least one additional vertex to one island to extend the island; moving at least one inter-island bridge from connecting between a first pair of vertices in respective ones of two islands to connecting between a second pair of vertices in respective ones of the two islands"]
removing, from the list R, all edges of the set B′ of edges; and [removing extraneous vertex (nodes) with bridge/edges ¶158]
removing, from the graph G′, the edge e. [prunes bridge (edge) and vertices with edges ¶158 " degree-1 pruning, in which an arbitrary bridge between two islands is removed followed by the removal of all extraneous vertices"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the qubit graph disclosed by Dudash and Adachi by incorporating the removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; removing, from the list R, all edges of the set B′ of edges; and removing, from the graph G′, the edge e disclosed by Coury because all techniques address the same field of machine learning and by incorporating Coury into Dudash and Adachi provides more efficient optimized embedding that uses less resources [Coury ¶24]
As to dependent claim 2, the rejection of claim 1 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ maps the nodes to qubits implemented in hardware. [Dudash vertices to qubits and ¶74-75 " embedding a QUBO problem into the hardware of a quantum annealer"…"vertices of the undirected graphs may represent the logical qubits while the edges may represent coupling between logical qubits."]
As to dependent claim 3, the rejection of claim 1 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ does not include any disconnected qubits. [Coury valid embedding only ¶56, vertex to qubits ¶42, removes extraneous vertex ¶150]
As to dependent claim 4, the rejection of claim 1 is incorporated, Dudash, Adachi and Coury further teach wherein qubits identified in the graph G′ are a minimum number of qubits needed in a real quantum annealer to solve a quadratic unconstrained binary optimization problem. [Adachi number of nodes being fewer and total qubits (minimum) ¶48, reduces graph ¶65, quantum annealing and optimization ¶32]
As to dependent claim 6, the rejection of claim 1 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ has fewer edges than the graph G. [Coury reduces edges in the target graph (fewer) ¶48]
As to dependent claim 9, the rejection of claim 1 is incorporated, Dudash, Adachi and Coury further teach wherein the adjacency criterion specifies that an edge that has at least one node with an adjacency degree equal to one should be removed from the graph G′. [Coury degree 1 pruning ¶158, singly-connected ¶150 and adjacency ¶145]
As to independent claim 11, Dudash teaches a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising: [storage medium, instructions and GPU ¶39]
creating a graph G′ by copying G; and [Dudash created a candidate local graph via copying ¶6 "copying the best local current graph to form a best local current graph copy, modifying the best local current graph copy to form a candidate local graph"]
for each of the edges e, performing, for as long as a stop criterion has not been met, operations comprising: [Dudash iterates graph until convergence (stop criterion) ¶95 " rather than using a fixed iteration number t, the system may instead apply one or more convergence conditions to determine when iterations should stop"]
identifying nodes and edges in the graph G′; [defines and identifies the graph with vertices (nodes) and edges ¶22, ¶75 "An undirected graph may be defined by a plurality of vertices (or nodes) and a plurality of edges that link respective pairs of vertices to one another"]
Dudash does not specifically teach ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R.
However, Adachi teaches ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R; [Adachi ordered (ranked) list of edges via graph embedding ¶84 "graph embedding technique"…"The list of all edges may be ordered or random"], [minor embedding ¶5]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the graph embedding disclosed by Dudash by incorporating the ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R disclosed by Adachi because both techniques address the same field of quantum computing and by incorporating Adachi into Dudash provides a better implement computationally efficient heuristic schemes that may be capable of operationally executing complex graph embedding into a particular quantum device [Adachi ¶8]
Dudash and Adachi do not specifically teach removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; removing, from the list R, all edges of the set B′ of edges; and removing, from the graph G′, the edge e.
However, Coury teaches removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; [prunes vertex with edges according to adjacency and moves them (places them into an intra-island edge set (B)) ¶37-38, ¶59, ¶48 "performing a degree-K pruning, wherein K is a positive integer; disconnecting at least one vertex from at least one island; connecting at least one additional vertex to one island to extend the island; moving at least one inter-island bridge from connecting between a first pair of vertices in respective ones of two islands to connecting between a second pair of vertices in respective ones of the two islands"]
removing, from the list R, all edges of the set B′ of edges; and [removing extraneous vertex (nodes) with bridge/edges ¶158]
removing, from the graph G′, the edge e. [prunes bridge (edge) and vertices with edges ¶158 " degree-1 pruning, in which an arbitrary bridge between two islands is removed followed by the removal of all extraneous vertices"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the qubit graph disclosed by Dudash and Adachi by incorporating the removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges; removing, from the list R, all edges of the set B′ of edges; and removing, from the graph G′, the edge e disclosed by Coury because all techniques address the same field of machine learning and by incorporating Coury into Dudash and Adachi provides more efficient optimized embedding that uses less resources [Coury ¶24]
As to dependent claim 12, the rejection of claim 11 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ maps the nodes to qubits implemented in hardware. [Dudash vertices to qubits and ¶74-75 " embedding a QUBO problem into the hardware of a quantum annealer"…"vertices of the undirected graphs may represent the logical qubits while the edges may represent coupling between logical qubits."]
As to dependent claim 13, the rejection of claim 11 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ does not include any disconnected qubits. [Coury valid embedding only ¶56, vertex to qubits ¶42, removes extraneous vertex ¶150]
As to dependent claim 14, the rejection of claim 11 is incorporated, Dudash, Adachi and Coury further teach wherein qubits identified in the graph G′ are a minimum number of qubits needed in a real quantum annealer to solve a quadratic unconstrained binary optimization problem. [Adachi number of nodes being fewer and total qubits (minimum) ¶48, reduces graph ¶65, quantum annealing and optimization ¶32]
As to dependent claim 16, the rejection of claim 11 is incorporated, Dudash, Adachi and Coury further teach wherein the graph G′ has fewer edges than the graph G. [Coury reduces edges in the target graph (fewer) ¶48]
As to dependent claim 19, the rejection of claim 11 is incorporated, Dudash, Adachi and Coury further teach wherein the adjacency criterion specifies that an edge that has at least one node with an adjacency degree equal to one should be removed from the graph G′. [Coury degree 1 pruning ¶158, singly-connected ¶150 and adjacency ¶145]
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Dudash in view of Adachi and Coury as applied to the rejection of claim 1 and 11 above, and further in view of Blainey et al. (US 5797012 A) hereinafter Blainey.
As to dependent claim 5, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the edges e are ranked according to their respective connection coefficient.
However, Blainey teaches wherein the edges e are ranked according to their respective connection coefficient. [edge ranks from high to low by weight (coefficient) Col. 4 ln. 37-47 " edges from a weighted graph are sorted from highest to lowest weight"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the edges e are ranked according to their respective connection coefficient disclosed by Blainey because all techniques address the same field of graph computing and by incorporating Blainey into Dudash, Adachi and Coury optimize the accuracy for consistent attributes in calculations [Blainey Col. 1 ln. 49-63].
As to dependent claim 15, the combination of Dudash, Adachi and Coury teach all the limitations of claim 11 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the edges e are ranked according to their respective connection coefficient.
However, Blainey teaches wherein the edges e are ranked according to their respective connection coefficient. [edge ranks from high to low by weight (coefficient) Col. 4 ln. 37-47 " edges from a weighted graph are sorted from highest to lowest weight"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the edges e are ranked according to their respective connection coefficient disclosed by Blainey because all techniques address the same field of graph computing and by incorporating Blainey into Dudash, Adachi and Coury optimize the accuracy for consistent attributes in calculations [Blainey Col. 1 ln. 49-63].
Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dudash in view of Adachi and Coury as applied to the rejection of claim 1 and 11 above, and further in view of Tucker et al. (US 20200084085 A1) hereinafter Tucker.
As to dependent claim 7, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e.
However, Tucker teaches wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. [pruning threshold that keeps strong parts of graph weights (coefficients) ¶27-28 " removing edges with weights below a pruning threshold"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury facilitate efficient response to computing events [Tucker ¶24],
As to dependent claim 8, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain.
However, Tucker teaches wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain. [minimum number/percent of edges ¶83 "minimum number or percentage of edges (e.g., at least 10 edges or at least 1% of remaining edges) in the most recent version of the graph"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury facilitate efficient response to computing events [Tucker ¶24],
As to dependent claim 17, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e.
However, Tucker teaches wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. [pruning threshold that keeps strong parts of graph weights (coefficients) ¶27-28 " removing edges with weights below a pruning threshold"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the stop criterion specifies a threshold for discarding a weak entanglement based on respective connection coefficients of the edges e. disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury facilitate efficient response to computing events [Tucker ¶24],
As to dependent claim 18, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain.
However, Tucker teaches wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain. [minimum number/percent of edges ¶83 "minimum number or percentage of edges (e.g., at least 10 edges or at least 1% of remaining edges) in the most recent version of the graph"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the stop criterion specifies a minimum number of edges that the graph G′ must contain disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury facilitate efficient response to computing events [Tucker ¶24],
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dudash in view of Adachi and Coury as applied to the rejection of claim 1 and 11 above, and further in view of Naccache et al. (US 20180129700 A1) hereinafter Naccache.
As to dependent claim 10, the combination of Dudash, Adachi and Coury teach all the limitations of claim 1 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the nodes and edges are identified using Tarjan's algorithm.
However, Naccache teaches wherein the nodes and edges are identified using Tarjan's algorithm. [Tarjan's algorithm for partitioning graph ¶108 "partition of a graph into strongly connected components can be determined exactly in linear time using for instance Tarjan's algorithm"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the nodes and edges are identified using Tarjan's algorithm disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury reduces the size of the graphs for efficient computing and storage costs [Naccache ¶9-10].
As to dependent claim 20, the combination of Dudash, Adachi and Coury teach all the limitations of claim 11 that are incorporated.
Dudash, Adachi and Coury do not specifically teach wherein the nodes and edges are identified using Tarjan's algorithm.
However, Naccache teaches wherein the nodes and edges are identified using Tarjan's algorithm. [Tarjan's algorithm for partitioning graph ¶108 "partition of a graph into strongly connected components can be determined exactly in linear time using for instance Tarjan's algorithm"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the embedding disclosed by Dudash, Adachi and Coury by incorporating the wherein the nodes and edges are identified using Tarjan's algorithm disclosed by Tucker because all techniques address the same field of graph computing and by incorporating Tucker into Dudash, Adachi and Coury reduces the size of the graphs for efficient computing and storage costs [Naccache ¶9-10].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Paredes Quiñones et al. (US 20240386263 A1) teaches model training with minor embedding to qubits and graphs (see ¶4-5).
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Beau Spratt whose telephone number is 571 272 9919. The examiner can normally be reached 8:30am to 5:00pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Welch can be reached at 571 272 7212. The fax phone number for the organization where this application or proceeding is assigned is 571 483 7388.
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/BEAU D SPRATT/ Primary Examiner, Art Unit 2143
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