Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in responses to the application filed on March 15,2024.
2. Claims 1-11 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 03/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 03/15/2024 are acceptable.
Specification
6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 8 recite “the output” of the first level shift circuit in lines 5 and 1 respectively. There is insufficient antecedent basis for these limitation.
Prior art Yasusaka “JP2017107551” is the considered to be the closest prior art. Yasusak discloses power supply regulator (Figs. 1-9) comprise a voltage control circuit ( controller 1100) comprising: a first power source line (Vin) connected to an output of a power supply device (Vin is coupled to battery); a shunt regulator having a reference voltage input ( control unit 3 compares Vref and detection circuit 20 is shunt regulator see page 6, lines 4-9) ; an output power source line (Vout) connected to the shunt regulator (control unit 3); a switch (switch 5) connected between the first power source line (Vin) and the output power source line (Vout) ; and a control circuit (34) connected to the first power source line (34 is coupled to Vin thru switch 5) and the output power source line (34 is coupled to Vout thru feedback) but fail having to disclose the claim limitation listed below.
Wu “CN 2169792” the invention relates to the technical field of charging and discharging circuit, specifically relates to a charging voltage control circuit.
Kato “20160020606” the present invention relates to generally to an electrostatic discharge protection circuit.
Allowable Subject Matter
8. Claims 1-5,7 and 9-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowed because the prior art in the record fails to discloses a voltage control circuit including the limitation “a control circuit connected to the first power source line and the output power source line, wherein the control circuit includes a generation circuit having an input receiving a signal related to a potential of the first power source line and an output, and configured to generate a control signal at the output from the signal received at the input, a first current source connected between the first power source line and the output power source line, a switch control circuit configured to generate a switch control signal for controlling the switch in response to the control signal from the output of the generation circuit, and connected between the first power source line and a second power source line different from the first power source line, and an enable generation circuit configured to generate an enable signal for controlling the shunt regulator in response to the control signal from the output of the generation circuit.”
Claim 11 is allowed because the prior art in the record fails to discloses a voltage control circuit including the limitation “after supplying the power, generating a signal having a voltage between the first power source line and a second power source line different from the first power source line by using a signal generation circuit connected between the first power source line and the second power source line; changing a potential of the output power source line by using a first current source connected between the output power source line and the first power source line; generating a first signal from the signal by using a first level shift circuit connected between the first power source line and the second power source line, the first signal being applied to a transfer circuit connected between the output power source line and the second power source line from the first level shift circuit and being level-shifted to a signal having a level to which the transfer circuit is capable of responding; inputting the first signal into the transfer circuit and generating a second signal generated when the first signal propagates through the transfer circuit at an output of the transfer circuit; level-shifting the second signal by using a second level shift circuit connected between the first power source line and the second power source line to generate a third signal; causing a shunt regulator connected to the output power source line to operate in response to the third signal, and controlling a voltage of the output power source line by using the shunt regulator; and closing the switch in response to the third signal to connect the first power source line and the output power source line to each other after the shunt regulator starts operating.”
Claim 12 is dependent on claim 11, thus is also allowed because of its dependency.
Note: Claims 6 and 8 would be allowable if rewritten or amended to overcome the rejection set forth in this office action.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838