Prosecution Insights
Last updated: April 19, 2026
Application No. 18/605,863

MICRO DISPLAY BACK PLANE SYSTEM AND PIXEL DRIVER CONTROLLER

Non-Final OA §102§103
Filed
Mar 15, 2024
Examiner
DANIELSEN, NATHAN ANDREW
Art Unit
2622
Tech Center
2600 — Communications
Assignee
Jade Bird Display (Shanghai) Limited
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
87%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
687 granted / 940 resolved
+11.1% vs TC avg
Moderate +14% lift
Without
With
+13.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
24 currently pending
Career history
964
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
53.8%
+13.8% vs TC avg
§102
22.5%
-17.5% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 940 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 5-7, 16, 18-21, 24, 27, 36, 39, 40, 42, 44-47, 50, 53, 56, and 57 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gu et al (US 2022/0044643; hereinafter Gu). • Regarding claim 1, Gu discloses a micro display back plane system (figure 2B) comprising: a data interface configured to provide image data as frame data (element 208 in figure 2B and ¶ 51); a display frame buffer coupled to the data interface to receive the frame data from the data interface frame by frame (inherent in element 212 in figure 2B and ¶ 51 for storing the data so that it may be processed); a column driver coupled to the display frame buffer to receive the frame data (element 202 in figure 2B and ¶ 52); and a pixel driver controller array coupled the column driver and configured to control pixels of a pixel display according to the frame data (elements 206 in figure 2B and ¶ 52; see also figure 5 and ¶ 69). • Regarding claim 7, Gu discloses a pixel driver controller (figure 12), comprising: a reference current source, configured to supply a reference current (elements 1270 and 1280 in figure 12 and ¶ 92); a current mirror source, coupled to receive the reference current, configured to provide a mirror current having a current value equal to a current value of the reference current (elements 1240, 1250, and 1260 in figure 12 and comprising elements 1245, 1255, and 1265, respectively; where, by its nature, a current mirror provides the same current on its output as is supplied to its input such that one of ordinary skill in the art would have reasonably known that ILED would be at least substantially the same as the current supplied by element 1270); at least two current switches, each coupled to the current mirror source to receive the mirror current, each current switch being further coupled to an LED device to control flow of the mirror current to the LED device (elements 1244, 1254, and 1264 in figure 12 and ¶ 92). • Regarding claim 16, Gu discloses a pixel driver controller (figure 12), comprising: a reference current source configured to supply a reference current (elements 1270 and 1280 in figure 12 and ¶ 92); at least two current mirror circuits (elements 1240, 1250, and 1260 in figure 12 and ¶ 92), each of the current mirror circuits comprising: a current mirror source (elements 1245, 1255, and 1265 in figure 12 and ¶ 92) and a current switch (elements 1244, 1254, and 1264 in figure 12 and ¶ 92), the current mirror source coupled in series to the current switch (note the relationship between at least elements 1244 and 1245 in figure 12); wherein the current mirror sources are configured to have respectively different current values (ILED, 1/4 ILED, and 1/16 ILED in figure 12 and ¶s 92 and 94); and each of the current switches is configured to control a power-on and power-off status of the corresponding current mirror circuit according to frame data (¶ 92); each current mirror circuit being further coupled to an LED device to control flow of the mirror current to the LED device (¶ 92). • Regarding claim 27, Gu discloses a micro display back plane system (figures 2B and 12), comprising: a data interface configured to provide image data as frame data (element 208 in figure 2B and ¶ 51); a display frame buffer coupled to the data interface to receive the frame data from the data interface frame by frame (inherent in element 212 in figure 2B and ¶ 51 for storing the data so that it may be processed); a column driver coupled to the display frame buffer to receive the frame data (element 202 in figure 2B and ¶ 52); and a pixel driver controller array coupled to the column driver and configured to control pixels of a pixel display according to the frame data (elements 206 in figure 2B and ¶ 52; see also figure 5 and ¶ 69), at least one pixel driver controller of the pixel driver controller array comprising: a reference current source, configured to supply a reference current (elements 1270 and 1280 in figure 12 and ¶ 92); a current mirror source, coupled to receive the reference current source, configured to provide a mirror current having a current value equal to a current value of the reference current (elements 1240, 1250, and 1260 in figure 12 and comprising elements 1245, 1255, and 1265, respectively; where, by its nature, a current mirror provides the same current on its output as is supplied to its input such that one of ordinary skill in the art would have reasonably known that ILED would be at least substantially the same as the current supplied by element 1270); and at least two current switches, each coupled to the current mirror source to receive the mirror current, each current switch being further coupled to an LED device to control flow of the mirror current to the LED device (elements 1244, 1254, and 1264 in figure 12 and ¶ 92). • Regarding claim 42, Gu discloses a micro display back plane system (figures 2B and 12), comprising: a data interface, configured to provide image data as frame data (element 208 in figure 2B and ¶ 51); a display frame buffer coupled to the data interface to receive the frame data from the data interface frame by frame (inherent in element 212 in figure 2B and ¶ 51 for storing the data so that it may be processed); a column driver coupled to the display frame buffer to receive the frame data (element 202 in figure 2B and ¶ 52); and a pixel driver controller array coupled to the column driver and configured to control pixels of a pixel display according to the frame data (elements 206 in figure 2B and ¶ 52; see also figure 5 and ¶ 69), at least one pixel driver controller of the pixel driver controller array comprises: a reference current source configured to supply a reference current (elements 1270 and 1280 in figure 12 and ¶ 92); at least two current mirror circuits (elements 1240, 1250, and 1260 in figure 12 and comprising elements 1245, 1255, and 1265, respectively), each of the current mirror circuits comprising: a current mirror source (elements 1245, 1255, and 1265 in figure 12 and ¶ 92) and a current switch (elements 1244, 1254, and 1264 in figure 12 and ¶ 92), the current mirror source coupled in series to the current switch (note the relationship between at least elements 1244 and 1245 in figure 12); wherein the current mirror sources are configured to have respectively different current values (ILED, 1/4 ILED, and 1/16 ILED in figure 12 and ¶s 92 and 94); and each of the current switches is configured to control a power-on and power-off status of the corresponding current mirror circuit according to frame data (¶ 92); and each current mirror circuit being further coupled to an LED device to control flow of the mirror current to the LED device (¶ 92). • Regarding claims 2, 5, 6, 18-21, 24, 36, 39, 40, 44-47, 50, 53, 56, and 57, Gu discloses everything claimed, as applied to claims 1, 16, 27, and 42. Additionally, Gu discloses where: Claims 2, 36, & 53: the micro display back plane system further comprises: an image enhancer coupled to the display frame buffer to receive and sharpen an image represented by the frame data (at least suggested by element 212 in figure 2B and ¶ 51). Claim 5, 39, & 56: the micro display back plane system further comprises: a power controller configured to control the system power for the back plane system (inherent in figures 2B, 5, and 12 for providing power to elements 500 and 1200). Claims 6, 40, & 57: the micro display back plane system further comprises: a row driver coupled to the pixel driver controller array and configured to control row scanning of the pixels to turn pixels on or off (element 204 in figure 2B and ¶ 52). Claims 18 & 44: the current value of each current mirror sources is an integer multiple of the reference current value (assuming 1/16 ILED in figure 12 as the reference current, 1/4 ILED is 4 times the reference current and ILED is 16 times the reference current). Claims 19 & 45: the current value of each of the current mirror sources is 2n times of the reference current, where n is a non-negative integer (assuming 1/16 ILED in figure 12 as the reference current, 1/4 ILED is 2 * 2 times the reference current and ILED is 2 * 8 times the reference current). Claims 20 & 46: the number of the current mirror sources is determined by a gray scale value of the frame data (¶s 66 and 92), the gray scale value of the frame data being an integer multiple of the number of the current mirror sources (¶s 92 and 94). Claims 21 & 47: the gray scale value of the frame data is N bit, N is a non-negative integer (¶s 66, 92, and 94). Claims 24 & 50: a transistor gate of each of the current mirror sources is coupled to a transistor gate of the reference current source (note the relationship between elements 1245, 1255, 1265, and 1280 in figure 12), and a transistor drain of the reference current source is coupled to the transistor gate of the reference current source (element 1280 in figure 12). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 4, 37, 38, 54, and 55 are rejected under 35 U.S.C. 103 as being unpatentable over Gu, in view of Yang et al (US 2021/0005169; hereinafter Yang). • Regarding claims 3, 4, 37, 38, 54, and 55, Gu discloses everything claimed, as applied to claims 1, 27, and 42. Additionally, Gu discloses where: Claims 3, 37, & 54: the image enhancer being coupled to transmit the optimized frame data to the column driver (¶ 51 and 52). However, Gu fails to disclose the additional details of the micro display back plane system. In the same field of endeavor, Yang discloses where: Claims 3, 37, & 54: the micro display back plane system further comprising: a one-time-programmable (“OTP”) memory coupled to the image enhancer and configured to determine a compensation value (element 111 in figure 5 and ¶ 81); the image enhancer is coupled to receive the compensation value from the OTP memory and optimize the frame data by applying the compensation value to the received frame data (¶ 81). Claims 4, 38, & 55: the OTP memory is coupled to the data interface and the display frame buffer to receive standard image data via the data interface and the frame data from the display frame buffer (figure 5), the OTP memory being further configured to determine the compensation value by comparing the standard image data with the frame data received from the display frame buffer (figure 5 and ¶s 81-83). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Gu according to the teachings of Yang, for the purposes of simplifying a system configuration, increasing the speed and/or reliability of the system, and reducing power consumption of the system (¶s 112-115). Claims 8-11, 14, 17, 25, 28-31, 34, 43, and 51 are rejected under 35 U.S.C. 103 as being unpatentable over Gu, in view of Lee (US 2021/0049957). • Regarding claims 8-11, 14, 17, 25, 28-31, 34, 43, and 51, Gu discloses everything claimed, as applied to claim 7. Additionally, Gu discloses where: Claims 9 & 29: a power-on status of each of the current switches corresponds to a state of conducting the mirror current (¶ 92), the power-on status of each of the current switches being determined by a gray scale value of the frame data (“brightness information” in ¶ 92); a gray scale of light emitted by the LED device is determined by the power-on status of each of the current switches (¶ 92). Claims 10 & 30: the number of the current switches is determined by the gray scale value of the frame data (¶s 66 and 92), the gray scale value of the frame data being an integer multiple of the number of the current switches (¶s 92 and 94). Claims 11 & 31: the gray scale value of the frame data is N bit, where N is a non-negative integer (¶s 66, 92, and 94). However, Gu fails to disclose the additional details of the pixel driver controller. In the same field of endeavor, Lee discloses where: Claims 8, 17, 28, & 43: the pixel driver controller further comprises: an internal memory configured to store frame data (element 403 in figure 6 and ¶s 77-80), each of the current switches being coupled to the internal memory to control operation of the current switches according to the frame data (inherent in the combination of Gu and Lee). Claim 14, 25, 34, & 51: the pixel driver controller further comprises: a global brightness controller coupled to each of the current switches to adjust the current of the LED device (element 505 in figure 6 and ¶s 85 and 86). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Gu according to the teachings of Lee, for the purpose of implementing a pixel circuit whereby power consumption is reduced and which has good matching characteristics (¶ 18). Claims 15, 26, 35, and 52 are rejected under 35 U.S.C. 103 as being unpatentable over Gu, in view of Lee, and further in view of Hsiao (US 2020/0341050). • Regarding claims 15, 26, 35, and 52, Gu, in view of Lee, discloses everything claimed, as applied to claims 14, 25, 34, and 51, respectively. However, Gu, in view of Lee, fails to disclose the additional details of the pixel driver controller. In the same field of endeavor, Hsiao discloses where the pixel driver controller further comprises a test circuit coupled between the LED device and the global brightness controller (figure 10 and ¶ 61). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Gu, as modified by Lee, according to the teachings of Hsiao, for the purpose of determining the quality of bonding of a micro light emitting device (¶ 61). Claims 41 and 58 are rejected under 35 U.S.C. 103 as being unpatentable over Gu, in view of Kobayashi et al (US 2019/0222774; hereinafter Kobayashi). • Regarding claims 41 and 58, Gu discloses everything claimed, as applied to claims 27 and 42, respectively. However, Gu fails to disclose the additional details of the micro display back plane system. In the same field of endeavor, Kobayashi discloses where the micro display back plane system further comprises a temperature sensor configured to detect temperature of the pixel driver controller array (elements 69 and 239 in figure 4 and ¶s 129 and 132-138). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Gu according to the teachings of Kobayashi, for the purpose of compensating for the temperature of a display (¶ 129). Allowable Subject Matter Claims 12, 13, 22, 23, 32, 33, 48, and 49 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest: a. In claims 12, 22, 32, and 48, where “the value of N is 8, the number of the current mirror sources is j, where j is an integer, and j=8/m, where m is a preset value that is 1, 2, or 4”, in combination with all the limitations in all the claims from which each depends. b. Claims 13, 23, 33, and 49 are objected to based on their dependence from one of claims 12, 22, 32, and 48. Closing Remarks/Comments Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached on (571) 272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Apr 15, 2025
Non-Final Rejection — §102, §103
Nov 14, 2025
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
87%
With Interview (+13.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 940 resolved cases by this examiner. Grant probability derived from career allow rate.

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