Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/25/2026 has been entered.
Claims 1, 3-8, 10-14, 16-20 are presented for Examination.
DETAILED ACTION
Claim Interpretation
Claim interpretation under 35 U.S.C. 112(f) for claims 1, 8 is maintained for the reasons presented in the previous office action. Applicant is reminded that claim interpretation under 35 U.S.C. 112(f) simply allows the claims to be read in conjunction with the underlying structure covered in the specification. It is not a claim rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8, 10-14, 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 1, 8, 14:
a) Claim recites “the plurality of voltage switching signals received by the packetizing module before the status of the bus changing from busy to ready are packetized to the packet by the packetizing module”. “, the terminologies are unclear and the use of this phrase which renders the claim indefinite because it is not clear whether the packetizing module receives the plurality of voltage switching signals and packetizing to the packet before the status of bus changing from busy to ready or whether the packetizing module is receiving the plurality of voltage switching signals before the status of the bus changing from busy to ready and then packetized to the packet. Specifically, it is not clear whether it is receiving the voltage switching signals before the bus is changing from busy to ready or packetizing the voltage switching signals to a packet before the bus is changing from busy to ready.
Examiner interprets as packetizing the voltage switching signals to a packet before the bus is changing from busy to ready.
Dependent claims 3-7, 10-13, 16-20 are rejected on the same basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 10-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kakkireni et.al. (U.S Patent Application Publication 2022/0413593; hereinafter “Kakkireni”; Reference cited as prior art in previous office action] in view of Lee et.al. (U.S Patent Application Publication 2011/0080914; hereinafter “Lee”; Reference cited as prior art in previous office action)
Regarding Claim 1, Kakkireni discloses , A processor for managing power, comprising:
a plurality of sub-systems[0044; “one of the chiplets 110a, 110b, 110c, and 110d may be configured as a master chiplet, and the remaining chiplets may be configured as slave chiplets. For example, the chiplet 110a may be configured as a master chiplet, and the chiplets 110b, 110c, and 110d may be configured as slave chiplets controlled by the chiplet 110a.”, 0057; Fig.1; ( i.e. slave chiplets corresponds to plurality of sub-systems)], wherein each of the plurality of sub-systems is configured to generate a voltage switching signal [0049; “..The sensors 116a, 116b, 116c, and 116d may measure thermal and electrical characteristics (i.e., provide temperature and voltage information) throughout each respective chiplet 110a, 110b, 110c, and 110d during testing and normal operating processes. Temperature values, voltage values, and/or power values measured by the sensors 116a, 116b, 116c, and 116d may be conveyed to each respective power controller 112a, 112b, 112c, and 112d for processing,..”, 0050; “ the power controllers 112a, 112b, 112c, and 112d may determine whether voltage micro-adjustments should be performed by the PMIC 102 based on the sensory information measured by the respective sensors 116a, 116b, 116c, and 116d…”, 0053;” voltage change messages generated by slave chiplet power controllers 112b, 112c, 112d and relayed to the slave chiplet communication interfaces 114b, 114c, 114d may be transmitted to the master chiplet communication interface 114a as soon as the voltage change messages are generated…”, 0059; ( i.e. the voltage change /adjustment message generated corresponds to the voltage switching signals of the respective subsystems)];
a packetizing module, coupled to the plurality of the sub-systems, wherein the packetizing module packetizes the plurality of voltage switching signals generated by the plurality of the sub-systems to a packet [0052-0053; “the master chiplet communication interface 114a may aggregate voltage change messages corresponding to independent, non-shared, power rails of the master chiplet 110a and the slave chiplets 110b, 110c, 110d, in addition to voltage change messages corresponding to power rails shared by the master chiplet 110a and the slave chiplets 110b, 110c, 110d...The slave chiplet communication interfaces 114b, 114c, 114d may transmit the voltage changes messages to the master chiplet communication interface 114a. The master chiplet communication interface 114a may generate one or more power rail adjustment messages based on the voltage change messages corresponding to independent power rails. The master chiplet communication interface 114a may transmit the power rail adjustment message(s) to the PMIC 102 to cause the PMIC to adjust an independent power rail of at least one of the master chiplet 110a, and the slave chiplets 110b, 110c, 110d”, 0061”.. the master chiplet communication interface 114a aggregates voltage change messages received from slave chiplet communication interfaces 114b, 114c, 114d, the master chiplet communication interface 114a may generate a single power rail adjustment message..”, 0062-0063;” a master-slave chiplet configuration in which one chiplet aggregates voltage change messages and generates a single power rail adjustment message to the PMIC may reduce the computation resources, and therefore total power consumption, needed to efficiently power the SIP 104 within the multiple-chiplet system 100.”, 0064;( i.e. the master chiplet coupled to the slave chiplets aggregates/ packetizes the voltage change messages from the slave chiplets via the master chiplet communication interface corresponds to the packetizing module)],
Wherein the packet includes a command for accessing a PMIC (power management integrated circuit) and a plurality of voltage switching data respectively corresponding to power switching requests of the plurality of the sub-system [0057; “the voltage change messages may be transmitted to each respective communication interface 114a, 114b, 114c, and 114d, and the slave chiplet communication interfaces 114b, 114c, and 114d may transmit the voltage change messages to the master chiplet communication interface 114a. Based on all received voltage change messages, the master chiplet communication interface 114a may generate and transmit a power rail adjustment message to the PMIC 102 causing the PMIC 102 to perform the following according to the present example: (i) increase voltage to a core via the CX power rail 120 and make no voltage adjustments across the MX power rail 118 for the master chiplet 110a; (ii) reduce voltage to a memory block via the MX power rail 118 and make no adjustments across the CX power rail 120 for the slave chiplet 110b; (iii) make no adjustments across the MX power rail 118 or the CX power rail 120 for the slave chiplet 110c; and (iv) decrease voltage to a core via the CX power rail 120 and increase voltage to a memory block via the MX power rail 118 for the slave chiplet 110d”, 0058; “ the master chiplet communication interface 114a may generate a single power rail adjustment message that may include at least one of the following instructions to the PMIC 102:..( i.e the message / packet includes instructions/ command to access the PMIC and PMIC adjusts the power rail of the master and/ or slave chiplets based on the voltage requests of the respective subsystems. Therefore, the power management message includes a command to access the PMIC and the voltage requests of the respective subsystems /Chiplets)] ; and
a PMIF (power management interface), configured to receive the packet and output the packet [“ The master chiplet communication interface 114a may aggregate received voltage change messages, which may include obtained sensory information and/or indications to increase or decreased a voltage, to develop a power rail adjustment message. The master chiplet communication interface 114a may transmit the power rail adjustment message to the PMIC 102 over the interface bus 106 (e.g., SPMI, I.sup.2C bus, etc.). The power rail adjustment message may include instructions for the PMIC 102 to make voltage micro-adjustments across the MX power rail 118 and/or the CX power rail 120 for each chiplet 110a, 110b, 110c, and 110d”, 0057; (i.e. The master chiplet communication interface corresponds to the PMIF/power management interface)].
wherein the packet is outputted to the PMIC via a bus [“… The master chiplet communication interface 114a may transmit the power rail adjustment message to the PMIC 102 over the interface bus 106 (e.g., SPMI, I.sup.2C bus, etc.)…”, 0057] and the plurality of voltage switching signals received by the packetizing module are packetized to the packet by the packetizing module[ 0053]
However, Kakkireni does not expressly disclose packetizing the voltage switching signals before the status of the bus changing from busy to ready. Specifically, Kakkireni discloses the plurality of voltage switching signals received by the packetizing module are packetized to the packet by the packetizing module and outputted via an interface bus, but does not expressly disclose the status of the bus (busy or ready).
In the same field of endeavor (e.g. a gateway apparatus and a serial communication unit to transmit the extracted data packet to the at least one target apparatus via a corresponding serial interface based on the serial interface information), Lee teaches,
Packetizing before the status of the bus changing from busy to ready [ “ Also, the managing of the group information including the plurality of target apparatuses may include setting the group information according to a characteristic of target apparatuses connected via each corresponding serial interface”, 0031; “…The packet distributor may transfer, to the serial communication unit, the serial interface information obtained from the group manager and list information associated with data to be transmitted to the target apparatuses”, 0074; “The serial communication unit may receive the data packet and the serial interface information from the packet distributor, and may transmit the data packet to at least one corresponding target apparatus via at least one serial interface based on the data packet and the serial interface information (S150).”, 0075 ;( i.e. packetizing the received data based on the group information to be transmitted to the respective target apparatuses); “ When data transmission to the target group via the serial interface is completed and a state of the corresponding serial interface is changed from a "BUSY" state to a "READY" state, the serial communication unit may inform the packet scheduler about the above change. Accordingly, the packet scheduler may inspect the buffer to verify whether transmittable data exists in the buffer, and may initiate again data transmission depending on the verification result.”, 0081;( i.e. when the status of the serial interface is “BUSY’, the packets are buffered and transmitted when it is in the Ready state. Hence before the status of the serial interface / bus changes to Ready state, the packets are not transmitted )].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kakkireni with Lee. Lee’s teaching of transmitting the packets to the target group based on the serial interface information/ state of the target group will substantially improve Kakkireni’s system to prevent packet loss and overflow of the buffer by determining the state of the interface / bus.
Regarding claims 3, 10, 16, Kakkireni discloses, wherein the packet is outputted to the PMIC by the PMIF[ 0057] (claims 3, 10, 16).
However, Kakkireni does not expressly disclose and outputting to the PMIC after the status of the bus changes from busy to ready. Specifically, Kakkireni does not expressly disclose the status of the bus (busy or ready).
Lee teaches, after the status of the bus changes from busy to ready[ “.. When all the serial interfaces are in a "READY" state (S215), the packet distributor may process the data to be transmitted to the target group via the serial communication unit (S220). In this instance, when other data stored in the buffer is simultaneously transmittable, the packet distributor may process the other data stored in the buffer to be simultaneously transmitted.”, 0080-0081; (i.e after the status of the serial interface/ bus is” Ready”, transmitting the packets)].
Regarding Claims 4, 15, Kakkireni discloses, wherein the PMIC further comprises a PMIC interface coupled to the PMIC interface, wherein the PMIC interface is configured to receive the packet via the bus [0057; “the voltage change messages may be transmitted to each respective communication interface 114a, 114b, 114c, and 114d, and the slave chiplet communication interfaces 114b, 114c, and 114d may transmit the voltage change messages to the master chiplet communication interface 114a. Based on all received voltage change messages, the master chiplet communication interface 114a may generate and transmit a power rail adjustment message to the PMIC 102 causing the PMIC 102 to perform the following according to the present example: (i) increase voltage to a core via the CX power rail 120 and make no voltage adjustments across the MX power rail 118 for the master chiplet 110a; (ii) reduce voltage to a memory block via the MX power rail 118 and make no adjustments across the CX power rail 120 for the slave chiplet 110b; (iii) make no adjustments across the MX power rail 118 or the CX power rail 120 for the slave chiplet 110c; and (iv) decrease voltage to a core via the CX power rail 120 and increase voltage to a memory block via the MX power rail 118 for the slave chiplet 110d”, 0058; . “ the master chiplet communication interface 114a may generate a single power rail adjustment message that may include at least one of the following instructions to the PMIC 102:..( i.e the message / packet includes instructions/ command to access the PMIC and PMIC adjusts the power rail of the master and/ or slave chiplets based on the voltage requests of the respective subsystems. Therefore, the power management message includes a command to access the PMIC and the voltage requests of the respective subsystems /Chiplets)] .
However, Kakkireni expressly disclose a PMIC comprising an un-packetizing module and the un-packetizing module un-packetizes the packet to the command and the plurality of voltage switching data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kakkireni to implement an un-packetizing module that un-packetizes the packet to a command and a plurality of voltage switching data as the PMIC adjusts the voltages to the chiplets according to the packaged voltage change message received from the master communication interface [ 0057-0058; 0062] to control power supplied to the chiplets across a shared power rail.
Regarding Claims 5, 11, 18, Kakkireni discloses, wherein the PMIC further comprises a plurality of voltage switching circuits coupled to the un-packetizing module, and the plurality of voltage switching circuits of the PMIC provide power to at least one of the plurality of the sub-systems according to the command and the plurality of voltage switching data generated from the packet un-packetized by the un-packetizing module [ 0054; 0057-0058].
Regarding Claims 6, Kakkireni discloses , the processor is a SoC (system on chip) and at least one of the plurality of sub-systems is at least one of: a CPU, a GPU, a modem, and a controller of a memory [ 0047-0048; 0233].
Regarding Claim 7, Kakkireni discloses , wherein the PMIF includes a SPMI (system power management interface) and the plurality of voltage switching signals are packetized [0057; 0235]
However, Kakkireni does not expressly disclose encoding according to a SPMI protocol.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kakkireni to encode according to a SPMI protocol as Kakkireni teaches an interface bus is a system power management interface (SPMI) that receives the packaged voltage change messages from the master chiplet and transmits to the PMIC[0057-0058;0235] . The PMIC adjusts the voltages to the chiplets according to the transmitted message. Hence encoding the message according to the interface/bus protocol to prevent any error.
Regarding Claims 12, 19, Kakkireni discloses , the processor is a SoC (system on chip) and at least one of the plurality of sub-systems is at least one of: a CPU, a GPU, a modem, and a controller of a memory [ 0047-0048; 0233].
Regarding claims 13, 20 , Kakkireni discloses wherein, the bus is coupled between a PMIF of the processor and a PMIC interface of the PMIC, and each of the PMIF and the PMIC interface includes a SPMI[0057;0235],
However, Kakkireni does not expressly disclose the plurality of voltage switching signals are packetized and un-packetized and/or encoded and decoded according to a SPMI protocol.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kakkireni to the plurality of voltage switching signals are packetized and un-packetized and/or encoded and decoded according to a SPMI protocol. [0057-0058;0235] as Kakkireni teaches an interface bus is a system power management interface (SPMI) that receives the packaged voltage change messages from the master chiplet and transmits to the PMIC[0057-0058;0235] . The PMIC adjusts the voltages to the chiplets according to the transmitted message by un-packetizing and decoding the message . Hence encoding / decoding the voltage change messages message according to the interface/bus protocol to prevent any error.
Regarding claims 8, 14, Kakkireni discloses, a power management system, comprising[ Fig.1]:
a processor, comprising[ “four chiplets 110a, 110b, 110c, and 110d located within a single system package..”, 0044; “The term “system-on-a-chip” (SoC) is used herein to refer to a set of interconnected electronic circuits typically, but not exclusively, including a processing device, a memory, and a communication interface. A processing device may include a variety of different types of processors 14 and processor cores, such as a general purpose processor, a central processing unit (CPU),..”, 0033] .
a plurality of sub-systems[0044; “one of the chiplets 110a, 110b, 110c, and 110d may be configured as a master chiplet, and the remaining chiplets may be configured as slave chiplets. For example, the chiplet 110a may be configured as a master chiplet, and the chiplets 110b, 110c, and 110d may be configured as slave chiplets controlled by the chiplet 110a.”, 0057; Fig.1; ( i.e. slave chiplets corresponds to plurality of sub-systems) ], wherein each of the plurality of sub-systems is configured to generate a voltage switching signal [0049; “..The sensors 116a, 116b, 116c, and 116d may measure thermal and electrical characteristics (i.e., provide temperature and voltage information) throughout each respective chiplet 110a, 110b, 110c, and 110d during testing and normal operating processes.,..”, 0050; “ the power controllers 112a, 112b, 112c, and 112d may determine whether voltage micro-adjustments should be performed by the PMIC 102 based on the sensory information measured by the respective sensors 116a, 116b, 116c, and 116d. ..The power controller 112a may create and transmit a voltage adjustment message, or voltage change message, to the communication interface 114a,…”, 0053;” voltage change messages generated by slave chiplet power controllers 112b, 112c, 112d and relayed to the slave chiplet communication interfaces 114b, 114c, 114d may be transmitted to the master chiplet communication interface 114a as soon as the voltage change messages are generated…”, 0059; ( i.e. the voltage change /adjustment message generated corresponds to the voltage switching signals of the respective slave subsystems)]
a packetizing module, coupled to the plurality of the sub-systems, wherein the packetizing module packetizes the plurality of voltage switching signals generated by the plurality of the sub-systems to a packet [0052-0053; “the master chiplet communication interface 114a may aggregate voltage change messages corresponding to independent, non-shared, power rails of the master chiplet 110a and the slave chiplets 110b, 110c, 110d, in addition to voltage change messages corresponding to power rails shared by the master chiplet 110a and the slave chiplets 110b, 110c, 110d...The slave chiplet communication interfaces 114b, 114c, 114d may transmit the voltage changes messages to the master chiplet communication interface 114a. The master chiplet communication interface 114a may generate one or more power rail adjustment messages based on the voltage change messages corresponding to independent power rails. The master chiplet communication interface 114a may transmit the power rail adjustment message(s) to the PMIC 102 to cause the PMIC to adjust an independent power rail of at least one of the master chiplet 110a, and the slave chiplets 110b, 110c, 110d”, 0061”.. the master chiplet communication interface 114a aggregates voltage change messages received from slave chiplet communication interfaces 114b, 114c, 114d, the master chiplet communication interface 114a may generate a single power rail adjustment message..”, 0062-0063;” a master-slave chiplet configuration in which one chiplet aggregates voltage change messages and generates a single power rail adjustment message to the PMIC may reduce the computation resources, and therefore total power consumption, needed to efficiently power the SIP 104 within the multiple-chiplet system 100.”, 0064;( i.e. the master chiplet coupled to the slave chiplets aggregates/ packetizes the voltage change messages from the slave chiplets via the master chiplet communication interface corresponds to the packetizing module)].; and
wherein the packet includes a command for accessing the PMIC and a plurality of voltage switching data respectively corresponding to power switching requests of the plurality of the sub-system [0057; “the voltage change messages may be transmitted to each respective communication interface 114a, 114b, 114c, and 114d, and the slave chiplet communication interfaces 114b, 114c, and 114d may transmit the voltage change messages to the master chiplet communication interface 114a. Based on all received voltage change messages, the master chiplet communication interface 114a may generate and transmit a power rail adjustment message to the PMIC 102 causing the PMIC 102 to perform the following according to the present example: (i) increase voltage to a core via the CX power rail 120 and make no voltage adjustments across the MX power rail 118 for the master chiplet 110a; (ii) reduce voltage to a memory block via the MX power rail 118 and make no adjustments across the CX power rail 120 for the slave chiplet 110b; (iii) make no adjustments across the MX power rail 118 or the CX power rail 120 for the slave chiplet 110c; and (iv) decrease voltage to a core via the CX power rail 120 and increase voltage to a memory block via the MX power rail 118 for the slave chiplet 110d”, 0058; . “ the master chiplet communication interface 114a may generate a single power rail adjustment message that may include at least one of the following instructions to the PMIC 102:..( i.e the message / packet includes instructions/ command to access the PMIC and PMIC adjusts the power rail of the master and/ or slave chiplets based on the voltage requests of the respective subsystems. Therefore, the power management message includes a command to access the PMIC and the voltage requests of the respective subsystems /Chiplets)] ;
a PMIF configured to receive the packet and output the packet[“ The master chiplet communication interface 114a may aggregate received voltage change messages, which may include obtained sensory information and/or indications to increase or decreased a voltage, to develop a power rail adjustment message. The master chiplet communication interface 114a may transmit the power rail adjustment message to the PMIC 102 over the interface bus 106 (e.g., SPMI, I.sup.2C bus, etc.). The power rail adjustment message may include instructions for the PMIC 102 to make voltage micro-adjustments across the MX power rail 118 and/or the CX power rail 120 for each chiplet 110a, 110b, 110c, and 110d”, 0057; (i.e. The master chiplet communication interface corresponds to the PMIF/power management interface)]; and
a PMIC comprising a PMIC interface coupled to the PMIC interface, wherein, the PMIC receives the packet outputted from the PMIF by the PMIC interface via a bus, [ 0005; “..The master chiplet communication interface 114a may transmit the power rail adjustment message to the PMIC 102 over the interface bus 106 (e.g., SPMI, I.sup.2C bus, etc.). The power rail adjustment message may include instructions for the PMIC 102 to make voltage micro-adjustments across the MX power rail 118 and/or the CX power rail 120 for each chiplet 110a, 110b, 110c, and 110d”, 0057;” …Based on all received voltage change messages, the master chiplet communication interface 114a may generate and transmit a power rail adjustment message to the PMIC 102 causing the PMIC 102 to perform the following according to the present example: (i) increase voltage to a core via the CX power rail 120 and make no voltage adjustments across the MX power rail 118 for the master chiplet 110a; (ii) reduce voltage to a memory block via the MX power rail 118 and make no adjustments across the CX power rail 120 for the slave chiplet 110b; (iii) make no adjustments across the MX power rail 118 or the CX power rail 120 for the slave chiplet 110c; and (iv) decrease voltage to a core via the CX power rail 120 and increase voltage to a memory block via the MX power rail 118 for the slave chiplet 110d.”, 0058; 0062;( i.e. the PMIC interfaces with the master and slave communication interfaces and the interface bus to receive the voltage change messages and send the voltage change adjustments across the power rails to the respective chiplets or subsystems according to the voltage requested by the chiplets)].
wherein the packet is outputted to the PMIC via a bus [“… The master chiplet communication interface 114a may transmit the power rail adjustment message to the PMIC 102 over the interface bus 106 (e.g., SPMI, I.sup.2C bus, etc.)…”, 0057] and the plurality of voltage switching signals received by the packetizing module are packetized to the packet by the packetizing module[ 0053]
However, Kakkireni does not expressly disclose a PMIC comprising an un-packetizing module and the un-packetizing module un-packetizes the packet to the command and the plurality of voltage switching data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kakkireni to implement an un-packetizing module that un-packetizes the packet to the command and the plurality of voltage switching data as the PMIC adjusts the voltages to the chiplets according to the packaged voltage change message received from the master communication interface [ 0057-0058; 0062] to control power supplied to the chiplets across a shared power rail.
However, Kakkireni does not expressly disclose packetizing the voltage switching signals before the status of the bus changing from busy to ready .Specifically, Kakkireni discloses the plurality of voltage switching signals received by the packetizing module are packetized to the packet by the packetizing module and outputted via an interface bus, but does not expressly disclose the status of the bus (busy or ready).
In the same field of endeavor (e.g. a gateway apparatus and a serial communication unit to transmit the extracted data packet to the at least one target apparatus via a corresponding serial interface based on the serial interface information), Lee teaches, Packetizing before the status of the bus changing from busy to ready [ “ Also, the managing of the group information including the plurality of target apparatuses may include setting the group information according to a characteristic of target apparatuses connected via each corresponding serial interface”, 0031; “…The packet distributor may transfer, to the serial communication unit, the serial interface information obtained from the group manager and list information associated with data to be transmitted to the target apparatuses”, 0074; “The serial communication unit may receive the data packet and the serial interface information from the packet distributor, and may transmit the data packet to at least one corresponding target apparatus via at least one serial interface based on the data packet and the serial interface information (S150).”, 0075 ;( i.e. packetizing the received data based on the group information to be transmitted to the respective target apparatuses); “ When data transmission to the target group via the serial interface is completed and a state of the corresponding serial interface is changed from a "BUSY" state to a "READY" state, the serial communication unit may inform the packet scheduler about the above change. Accordingly, the packet scheduler may inspect the buffer to verify whether transmittable data exists in the buffer, and may initiate again data transmission depending on the verification result.”, 0081;( i.e. when the status of the serial interface is “BUSY’, the packets are buffered and transmitted when it is in the Ready state. Hence before the status of the serial interface / bus changes to Ready state, the packets are not transmitted )].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kakkireni with Lee. Lee’s teaching of transmitting the packets to the target group based on the serial interface information/ state of the target group will substantially improve Kakkireni’s system to prevent packet loss and overflow of the buffer by determining the state of the interface / bus.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, 14 have been considered
but are moot because the arguments do not apply as setforth in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Frank., U.S Patent Application Publication 2008/0144495, teaches Early multilink traffic throttling for a data communication node throttles packets designated for forwarding on a multilink interface of a data communication node before distributing the packets to output queues associated with physical links of the multilink interface so as to prevent packet loss and reassembly problems caused by non-uniform operational characteristics of the physical links, such as disparate line rates. More particularly, early multilink traffic throttling verifies that all output queues associated with physical links of a multilink interface are ready to receive a packet before distributing the packet.
Jayakrishnan et al., U.S Patent Application Publication 2005/0141429, teaches, a method includes receiving on a first switching device a message from a second switching device that indicates to slow packet transmission to the second switching device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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